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| this is information on a product in full production. september 2014 docid024995 rev 3 1/105 stm32l100rc ultra-low-power 32b mcu arm ? -based cortex ? -m3, 256kb flash, 16kb sram, 4kb eeprom, lcd, usb, adc, dac, memory i/f datasheet ? production data features ? ultra-low-power platform ? 1.65 v to 3.6 v power supply ? -40 c to 105 c temperature range ? 0.29 a standby mode (3 wakeup pins) ? 1.15 a standby mode + rtc ? 0.44 a stop mode (16 wakeup lines) ? 1.4 a stop mode + rtc ? 8.6 a low-power run mode ? 185 a/mhz run mode ?10 na ultra-low i/o leakage ?8 s wakeup time ? core: arm ? cortex ? -m3 32-bit cpu ? from 32 khz up to 32 mhz max ? 1.25 dmips/mhz (dhrystone 2.1) ? memory protection unit ? reset and supply management ? low power, ultrasafe bor (brownout reset) with 5 selectable thresholds ? ultra-low-power por/pdr ? programmable voltage detector (pvd) ? clock sources ? 1 to 24 mhz crystal oscillator ?32 khz oscillator for rtc with calibration ? high speed internal 16 mhz ? internal low power 37 khz rc ? internal multispeed low power 65 khz to 4.2 mhz ? pll for cpu clock and usb (48 mhz) ? pre-programmed bootloader ? usb and usart supported ? development support ? serial wire debug supported ? jtag supported ? 51 fast i/os (42 i/os 5v tolerant), all mappable on 16 external interrupt vectors ? memories ? 256 kb flash with ecc ?16 kb ram ?4 kb of true eeprom with ecc ?20 b backup register ? lcd driver for up to 8x28 segments ? analog peripherals ? 12-bit adc 1msps up to 20 channels ? 12-bit dacs 2 channels with output buffers ? 2x ultra-low-power-comparators (window mode and wake up capability) ? dma controller 12x channels ? 9x peripherals communication interface ? 1xusb 2.0 (internal 48 mhz pll) ? 3xusart ? 3xspi 16 mbits/s (2x spi with i2s) ? 2xi2c (smbus/pmbus) ? 10x timers: 6x 16-bit with up to 4 ic/oc/pwm channels, 2x 16-bit basic timer, 2x watchdog timers (independent and window) ? crc calculation unit lqfp64 (10 10 mm) www.st.com
contents stm32l100rc 2/105 docid024995 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 arm cortex-m3 core with mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22 3.6 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 dma (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25 3.13 system configuration controller and routing interface . . . . . . . . . . . . . . . 25 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.2 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 docid024995 rev 3 3/105 stm32l100rc 4 3.14.3 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) . . 27 3.15.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.4 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 27 3.17 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.7 optional lcd power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.8 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.2 embedded reset and power control block characteristics . . . . . . . . . . . 45 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.5 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 contents stm32l100rc 4/105 docid024995 rev 3 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.15 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.16 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.17 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.18 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.19 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.20 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.21 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 docid024995 rev 3 5/105 stm32l100rc 6 list of tables table 1. ultra-low-power stm32l100rc device features and peripheral counts . . . . . . . . . . . . . . 10 table 2. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14 table 3. cpu frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15 table 4. functionalities depending on the working mode (from run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. stm32l100rc pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 13. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 16. current consumption in run mode, code with data processing running from flash. . . . . . 49 table 17. current consumption in run mode, code with data processing running from ram . . . . . . 50 table 18. current consumption in sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 19. current consumption in low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 20. current consumption in low-power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 21. typical and maximum current consumptions in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 56 table 23. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 24. low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 25. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 28. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 29. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 30. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 31. msi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 32. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 33. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 34. flash memory and data eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 35. flash memory and data eeprom endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 69 table 36. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 37. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 38. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 40. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 42. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 43. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 44. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 45. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 46. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 47. scl frequency (f pclk1 = 32 mhz, v dd = vdd_i2c = 3.3 v). . . . . . . . . . . . . . . . . . . . . . . . 79 list of tables stm32l100rc 6/105 docid024995 rev 3 table 48. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 49. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 50. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 51. usb: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 52. i2s characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 53. adc clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 54. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 56. maximum source impedance r ain max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 57. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 58. operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 59. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 60. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 61. lcd controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 62. lqfp64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . . 99 table 63. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 64. stm32l100rc ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 65. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 docid024995 rev 3 7/105 stm32l100rc 7 list of figures figure 1. ultra-low-power stm32l100rc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3. stm32l100rc lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 5. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 6. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 8. optional lcd power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 9. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 10. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 12. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 13. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 14. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 15. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 16. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 17. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 18. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 19. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 20. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 21. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 22. i 2 s master timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 23. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 24. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 25. maximum dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 26. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 27. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 98 figure 28. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 29. thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 30. thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 introduction stm32l100rc 8/105 docid024995 rev 3 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32l100rc ultra-low-power arm ? cortex ? -m3 based microcontroller product line. the ultra-low-power stm32l100rc device is a microcontroller of 256 kbytes in a 64-pin package. the description below gives an overview of the complete range of peripherals proposed in this device. these features make the ultra-low-power stm32l100rc microcontroller suitable for a wide range of applications: ? medical and handheld equipment ? application control and user interface ? pc peripherals, gaming, gps and sport equipment ? alarm systems, wired and wireless sensors, video intercom ? utility metering this stm32l100rc datasheet should be read in conjunction with the stm32l1xxxx reference manual (rm0038). the application note ?getting started with stm32l1xxx hardware development? (an3216) gives a hardware implementation overview. both documents are available from the stmicroelectronics website www.st.com. for information on the arm ? cortex ? -m3 core please refer to the arm ? cortex ? -m3 technical reference manual, available from the www.arm.com website. figure 1 shows the general block diagram of the device. docid024995 rev 3 9/105 stm32l100rc 39 2 description the ultra-low-power stm32l100rc device incorporates the connectivity power of the universal serial bus (usb) with the high-performance arm ? cortex ? -m3 32-bit risc core operating at a frequency of 32 mhz (33.3 dmips), a memory protection unit (mpu), high- speed embedded memories (flash memory up to 256 kbytes and ram up to 16 kbytes) and an extensive range of enhanced i/os and peripherals connected to two apb buses. the stm32l100rc device offers one 12-bit adc, two dacs, two ultra-low-power comparators, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. moreover, the stm32l100rc device contains standard and advanced communication interfaces: up to two i2cs, three spis, two i2s, three usar ts, and an usb. they also include a real-time clock and a set of backup registers that remain powered in standby mode. finally, the integrated lcd controller has a built-in lcd voltage generator that allows you to drive up to 8 multiplexed lcds with contrast independent of the supply voltage. the ultra-low-power stm32l100rc device operates from a 1.8 to 3.6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. they are available in the -40 to +85 c and -40 to +105 c temperature ranges. a comprehensive set of power-saving modes allows the design of low-power applications. description stm32l100rc 10/105 docid024995 rev 3 2.1 device overview 2.2 ultra-low-power device continuum the ultra-low-power family offers a large choice of cores and features. from proprietary 8- bit to up to cortex-m3, including the cortex-m0+, the stm32lx series are the best choice to answer your needs, in terms of ultra-low-power features. the stm32 ultra-low-power series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare, wearable applications. several built-in features like lcd drivers, dual-bank table 1. ultra-low-power stm32l100rc device features and peripheral counts peripheral stm32l100rc flash (kbytes) 256 data eeprom (kbytes) 4 ram (kbytes) 16 16-bit timers general- purpose 6 basic 2 communica tion interfaces spi/(i2s) 3 / (2) i 2 c 2 usart 3 usb 1 gpios 51 12-bit synchronized adc number of channels 1 20 12-bit dac number total of channels 2 2 lcd com x seg 4x32 or 8x28 comparators 2 max. cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v operating temperatures ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: ?40 to + 110 c package lqfp64 docid024995 rev 3 11/105 stm32l100rc 39 memory, low-power run mode, op-amp, aes 128-bit, dac, usb crystal-less and many others will clearly allow you to build very cost-optimized applications by reducing bom. note: stmicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any stm8lx and stm32lx devices and between any of the stm32lx and stm32fx series. thanks to this unprecedented scalability, your old applications can be upgraded to respond to the latest market features and efficiency demand. 2.2.1 performance all families incorporate highly energy-efficient cores with both harvard architecture and pipelined execution: advanced stm8 core for stm8l families and arm cortex-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultra-low-power performance to range from 5 up to 33.3 dmips. 2.2.2 shared peripherals stm8l15xxx, stm32l15xxx and stm32l162xx share identical peripherals which ensure a very easy migration from one family to another: ? analog peripherals: adc, dac and comparators ? digital peripherals: rtc and some communication interfaces 2.2.3 common system strategy. to offer flexibility and optimize performance, the stm8l15xxx, stm32l15xxx and stm32l162xx family uses a common architecture: ? same power supply range from 1.65 v to 3.6 v ? architecture optimized to reach ultra-low consumption both in low-power modes and run mode ? fast startup strategy from low-power modes ? flexible system clock ? ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector 2.2.4 features st ultra-low-power continuum also lies in feature compatibility: ? more than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm ? memory density ranging from 2 to 512 kbytes functional overview stm32l100rc 12/105 docid024995 rev 3 3 functional overview figure 1. ultra-low-power stm32l100rc block diagram 0 6 y 9 3 2 : ( 5 9 2 / 7 5 ( * e l w $ ' & ( ; 7 , 7 : . 8 3 : l q : $ 7 & + ' 2 * - 7 $ * 6 : ) p d [ 0 + ] - 7 ' , 1 - 7 5 6 7 1 5 6 7 8 6 % ) 6 g h y l f h 6 5 $ 0 . [ [ e l w , & 7 , 0 ( 5 7 , 0 ( 5 ; 7 $ / 2 6 & 0 + ] ; 7 $ / n + ] ( ( 3 5 2 0 % l w % d f n x s l q w h u i d f h 7 , 0 ( 5 5 7 & 9 $ : 8 5 & + 6 , r e o 8 6 % 6 5 $ 0 % 8 6 $ 5 7 8 6 $ 5 7 6 3 , , 6 [ % l w % d f n x s 5 h j , & 8 6 $ 5 7 5 & 0 6 , 6 w d q g e \ l q w h u i d f h : ' * . % 2 5 % j d s 6 3 , , ) # 9 ' ' $ 3 9 ' * 3 , 2 3 g 5 7 & * 3 , 2 3 2 5 7 ' * 3 , 2 3 2 5 7 + / & ' [ [ e l w ' $ & ) , ) , , ) e l w ' $ & ' $ & b 2 8 7 d v $ ) ' $ & b 2 8 7 d v $ ) 0 3 8 * 3 & r p s 3 8 3 ' 3 ' 5 3 ' 5 7 , 0 ( 5 7 , 0 ( 5 * h q h u d o s x u s r v h w l p h u v / & ' % r r v w h u 5 & / 6 , 7 , 0 ( 5 6 e l w v [ [ e l w 6 3 , , 6 6 \ v w h p 6 x s s o \ p r q l w r u l q j # 9 ' ' $ # 9 ' ' $ # 9 ' ' $ # 9 ' ' $ 6 x s s o \ p r q l w r u l q j * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 $ $ 3 % ) p d [ 0 + ] $ 3 % ) p d [ 0 + ] 3 / / & o r f n 0 j p w 5 7 & b 2 8 7 $ + % $ 3 % $ + % $ 3 % - 7 & . 6 : & / . - 7 0 6 6 : ' $ 7 - 7 ' 2 d v $ ) . % 3 5 2 * 5 $ 0 . % ' $ 7 $ . % % 2 2 7 # 9 ' ' 9 ' ' & 2 5 ( 9 u h i 0 & 3 8 * 3 ' 0 $ f k d q q h o v * 3 ' 0 $ f k d q q h o v $ + % 3 & / . $ 3 % 3 & / . + & / . ) & / . # 9 ' ' 9 ' ' 9 w r 9 9 v v 2 6 & b , 1 2 6 & b 2 8 7 7 $ 0 3 ( 5 f k d q q h o v f k d q q h o v f k d q q h o v f k d q q h o v 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 : 6 & . 0 & . 6 ' d v $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 : 6 & . 0 & . 6 ' d v $ ) 6 & / 6 ' $ $ v $ ) 6 & / 6 ' $ 6 0 % x v 3 0 % x v $ v $ ) 8 6 % b ' 3 8 6 % b ' 0 6 ( * [ & 2 0 [ & 2 0 3 [ b , 1 [ 9 ' ' $ 9 6 6 $ 3 $ > @ $ ) 3 % > @ 3 & > @ 3 ' > @ 3 + > @ 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 f k d q q h o v f k d q q h o f k d q q h o 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) $ ) l e x v ' e x v % 2 5 , q w $ + % ) p d [ 0 + ] % x v 0 d w u l [ 0 6 9 / & ' 9 w r 9 9 / & ' # 9 ' ' 2 6 & b , 1 2 6 & b 2 8 7 1 9 , & ( ( 3 5 2 0 , q w h u i d f h docid024995 rev 3 13/105 stm32l100rc 39 3.1 low-power modes the ultra-low-power stm32l100rc supports dynamic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply. there are three power consumption ranges: ? range 1 (v dd range limited to 2.0 v - 3.6 v), with the cpu running at up to 32 mhz ? range 2 (full v dd range), with a maximum cpu frequency of 16 mhz ? range 3 (full v dd range), with a maximum cpu frequency limited to 4 mhz (generated only with the multispeed internal rc oscillator clock source) seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. sleep mode power consumption at 16 mhz is about 1 ma with all peripherals off. ? low-power run mode this mode is achieved with the multispeed internal (msi) rc oscillator set to the minimum clock (131 khz), execution from sram or flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. in low- power run mode, the clock frequency and the number of enabled peripherals are both limited. ? low-power sleep mode this mode is achieved by entering sleep mode with the internal voltage regulator in low power mode to minimize the regulator?s operating current. in low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. ? stop mode with rtc stop mode achieves the lowest power consumption while retaining the ram and register contents and real time clock. all clocks in the v core domain are stopped, the pll, msi rc, hsi rc and hse crystal oscillators are disabled. the lse or lsi is still running. the voltage regulator is in the low-power mode. the device can be woken up from stop mode by any of the exti line, in 8 s. the exti line source can be one of the 16 external lines. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on), it can be the rtc alarm(s), the usb wakeup, the rtc tamper events, the rtc timestamp event or the rtc wakeup. functional overview stm32l100rc 14/105 docid024995 rev 3 ? stop mode without rtc stop mode achieves the lowest power consumption while retaining the ram and register contents. all clocks are stopped, the pll, msi rc, hsi and lsi rc, lse and hse crystal oscillators are disabled. the voltage regulator is in the low-power mode. the device can be woken up from stop mode by any of the exti line, in 8 s. the exti line source can be one of the 16 external lines. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). it can also be wakened by the usb wakeup. ? standby mode with rtc standby mode is used to achieve the lowest power consumption and real time clock. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi rc and hse crystal oscillators are also switched off. the lse or lsi is still running. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc_csr). the device exits standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event occurs. ? standby mode without rtc standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi and lsi rc, hse and lse crystal oscillators are also switched off. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc_csr). the device exits standby mode in 60 s when an external reset (nrst pin) or a rising edge on one of the three wkup pin occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped automatically by entering stop or standby mode. table 2. functionalities depending on the operating power supply range functionalities depending on the operating power supply range operating power supply range dac and adc operation usb dynamic voltage scaling range i/o operation v dd = 1.8 to 2.0 v conversion time up to 500 ksps not functional range 2 or range 3 degraded speed performance v dd = 2.0 to 2.4 v conversion time up to 500 ksps functional (1) 1. to be usb compliant from the io voltage standpoint, the minimum v dd is 3.0 v. range 1, range 2 or range 3 full speed operation v dd = 2.4 to 3.6 v conversion time up to 1 msps functional (1) range 1, range 2 or range 3 full speed operation docid024995 rev 3 15/105 stm32l100rc 39 table 3. cpu frequency range depending on dynamic voltage scaling cpu frequency range dynamic voltage scaling range 16 mhz to 32 mhz (1ws) 32 khz to 16 mhz (0ws) range 1 8 mhz to 16 mhz (1ws) 32 khz to 8 mhz (0ws) range 2 2.1mhz to 4.2 mhz (1ws) 32 khz to 2.1 mhz (0ws) range 3 functional overview stm32l100rc 16/105 docid024995 rev 3 table 4. functionalities depending on the working mode (from run/active down to standby) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability cpu y -- y -- -- -- -- -- flash y y y y -- -- -- -- ram y y y y y -- -- -- backup registers y y y y y -- y -- eeprom y y y y y -- -- -- brown-out rest (bor) yyyyyyy-- dma y y y y -- -- -- -- programmable voltage detector (pvd) yyyyyyy-- power on reset (por) yyyyyyy-- power down rest (pdr) yyyyy--y-- high speed internal (hsi) y y -- -- -- -- -- -- high speed external (hse) y y -- -- -- -- -- -- low speed internal (lsi) yyyyy------ low speed external (lse) yyyyy------ multi-speed internal (msi) y y y y -- -- -- -- inter-connect controller y y y y -- -- -- -- rtc y y y y y y y -- rtc tamper y y y y y y y y auto wakeup (awu) yyyyyyyy lcd y y y y y -- -- -- usb y y -- -- -- y -- -- usart y y y y y (1) -- -- spi y y y y -- -- -- -- i2c y y y y -- (1) -- -- docid024995 rev 3 17/105 stm32l100rc 39 3.2 arm cortex-m3 core with mpu the arm cortex-m3 processor is the industry leading processor for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit device. adc y y -- -- -- -- -- -- dac y y y y y -- -- -- tempsensor y y y y y -- -- -- op amp y y y y y -- -- -- comparators y y y y y y -- -- 16-bit and 32-bit timers y y y y -- -- -- -- iwdg y y y y y y y y wwdg y y y y -- -- -- -- touch sensing y y -- -- -- -- -- -- systic timer y y y y -- -- -- gpios y y y y y y -- 3 pins wakeup time to run mode 0 s 0.4 s3 s46 s < 8 s58 s consumption v dd =1.8 to 3.6 v (typ) down to 185 a/mhz (from flash) down to 34.5 a/mhz (from flash) down to 8.6 a down to 4.4 a 0.43 a (no rtc) v dd =1.8v 0.29 a (no rtc) v dd =1.8v 1.15 a (with rtc) v dd =1.8v 0.9 a (with rtc) v dd =1.8v 0.44 a (no rtc) v dd =3.0v 0.29 a (no rtc) v dd =3.0v 1.4 a (with rtc) v dd =3.0v 1.15 a (with rtc) v dd =3.0v 1. the startup on communication line wakes the cpu which was made possible by an exti, this induces a delay before entering run mode. table 4. functionalities depending on the working mode (from run/active down to standby) (continued) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability functional overview stm32l100rc 18/105 docid024995 rev 3 the memory protection unit (mpu) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. it provides up to eight different regions and an optional predefined background region. owing to its embedded arm core, the stm32l100rc is compatible with all arm tools and software. nested vectored interrupt controller (nvic) the ultra-low-power stm32l100rc embeds a nested vectored interrupt controller able to handle up to 52 maskable interrupt channels (not including the 16 interrupt lines of arm cortex-m3) and 16 priority levels. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving , higher-priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 reset and supply management 3.3.1 power supply schemes ? v dd = 1.65 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 1.8 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. the device exists in two versions: ? the version with bor activated at power-on operates between 1.8 v and 3.6 v. ? the other version without bor operates between 1.65 v and 3.6 v. after the v dd threshold is reached (1.65 v or 1.8 v depending on the bor which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the bor permanently: in this case, the v dd min value becomes 1.65 v (whatever the version, bor active or not, at power-on). when bor is active at power-on, it ensures proper operation starting from 1.8 v whatever the power ramp-up phase before it reaches 1.8 v. when bor is not active at power-up, the docid024995 rev 3 19/105 stm32l100rc 39 power ramp-up should guarantee that 1.65 v is reached on v dd at least 1 ms after it exits the por area. five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possible to automatically switch off the internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms when bor is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for device with bor inactive at power-up. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the regulator has three operation modes: main (mr), low-power (lpr) and power down. ? mr is used in run mode (nominal regulation) ? lpr is used in the low-power run, low-power sleep and stop modes ? power down is used in standby mode. the regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and ram are lost except for the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc_csr). 3.3.4 boot modes at startup, boot pins are used to select one of three boot options: ? boot from flash memory ? boot from system memory ? boot from embedded ram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 and usart2. see application note ?stm32 microcontroller system memory boot mode? (an2606) for details. functional overview stm32l100rc 20/105 docid024995 rev 3 3.4 clock management the clock controller distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. it features: ? clock prescaler : to get the best trade-off between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source : three different clock sources can be used to drive the master clock sysclk: ? 1-24 mhz high-speed external crystal (hse), that can supply a pll ? 16 mhz high-speed internal rc oscillator (hsi), trimmable by software, that can supply a pll ? multispeed internal rc oscillator (msi), trimmable by software, able to generate 7 frequencies (65 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz, 4.2 mhz). when a 32.768 khz clock source is available in the system (lse), the msi frequency can be trimmed by software down to a 0.5% accuracy. ? auxiliary clock source : two ultra-low-power clock sources that can be used to drive the lcd controller and the real-time clock: ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measured using the high-speed internal rc oscillator for greater precision. ? rtc and lcd clock sources: the lsi, lse or hse sources can be chosen to clock the rtc and the lcd, whatever the system clock. ? usb clock source: the embedded pll has a dedicated 48 mhz clock output to supply the usb interface. ? startup clock : after reset, the microcontroller restarts by default with an internal 2 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master clock is automatically switched to hsi and a software interrupt is generated if enabled. ? clock-out capability (mco: microcontroller clock output): it outputs one of the internal clocks for external use by the application. several prescalers allow the configuration of the ahb frequency, each apb (apb1 and apb2) domains. the maximum frequency of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree. docid024995 rev 3 21/105 stm32l100rc 39 figure 2. clock tree 1. for the usb function to be available, both hse and pll must be enabled, with the cpu running at either 24 mhz or 32 mhz. - 3 6 , 3 ) 2 # , 3 % / 3 # ( 3 ) 2 # ( 3 % / 3 # 6 6 $ $ # / 2 % 6 l e v e l s h i f t e r s l e v e l s h i f t e r s 2 4 # 0 , , 8 6 l e v e l s h i f t e r s , 3 % t e m p o - ( z c l o c k d e t e c t o r 6 , 3 7 a t c h d o g c k ? p l l i n s o u r c e c o n t r o l # l o c k 7 a t c h d o g e n a b l e 2 4 # e n a b l e c k ? h s i c k ? h s e ( 3 % p r e s e n t o r n o t , 3 ) t e m p o c k ? p l l ! ( " p r e s c a l e r ! 0 " ! 0 " c k ? u s b 6 c o 6 c o m u s t b e a t - ( z # + ? 4 ) - 3 9 3 # + ? # 0 5 # + ? & # , + # + ? 0 7 2 # + ? 5 3 " # + ? 4 ) - 4 ' / # + ? ! 0 " # + ? ! 0 " u s b e n a n d n o t d e e p s l e e p t i m e r e n a n d n o t d e e p s l e e p a p b p e r i p h e n a n d n o t d e e p s l e e p a p b p e r i p h e n a n d n o t d e e p s l e e p n o t s l e e p o r d e e p s l e e p n o t s l e e p o r d e e p s l e e p n o t d e e p s l e e p n o t d e e p s l e e p 3 t a n d b y s u p p l i e d v o l t a g e d o m a i n 3 y s t e m c l o c k - # / i f ! 0 " p r e s c x e l s e x c k ? l s e # + ? , # $ - ( z 6 $ $ # / 2 % 6 $ $ # / 2 % 6 $ $ # / 2 % , # $ e n a b l e - 3 ) 2 # 6 6 $ $ # / 2 % l e v e l s h i f t e r s c k ? m s i c k ? l s i # + ? ! $ # ! $ # e n a b l e , 3 , 3 , 3 , 3 , 3 , 3 p r e s c a l e r p r e s c a l e r functional overview stm32l100rc 22/105 docid024995 rev 3 3.5 low-power real-time clock and backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. the rtc provides two programmable alarms and programmable periodic interrupts with wakeup from stop and standby modes. the programmable wakeup time ranges from 120 s to 36 hours. the rtc can be calibrated with an external 512 hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. the rtc can also be automatically corrected with a 50/60hz stable powerline. the rtc calendar can be updated on the fly down to sub second precision, which enables network system synchronization. a time stamp can record an external event occurrence, and generates an interrupt. there are twenty 32-bit backup registers provided to store 80 bytes of user application data. they are cleared in case of tamper detection. three pins can be used to detect tamper events. a change on one of these pins can reset backup register and generate an interrupt. to prevent false tamper event, like esd event, these three tamper inputs can be digitally filtered. 3.6 gpios (general-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated afio registers. all gpios are high current capable. the alternate function configuration of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to the ahb with a toggling speed of up to 16 mhz. external interrupt/event controller (exti) the external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 83 gpios can be connected to the 16 external interrupt lines. the 8 other lines are connected to rtc, pvd, usb, comparator events or capacitive sensing acquisition. docid024995 rev 3 23/105 stm32l100rc 39 3.7 memories the stm32l100rc device has the following features: ? 16 kbytes of embedded ram accessed (read/write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, operating the ram does not lead to any performance penalty during accesses to the system bus (ahb and apb buses). ? the non-volatile memory is divided into three arrays: ? 128 kbytes of embedded flash program memory ? 4 kbytes of data eeprom ? options bytes the options bytes are used to write-protect or read-out protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (arm cortex-m3 jtag and serial wire) and boot in ram selection disabled (jtag fuse) the whole non-volatile memory embeds the error correction code (ecc) feature. 3.8 dma (direct memory access) the flexible 12-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, dac and adc. 3.9 lcd (liquid crystal display) the lcd drives up to 8 common terminals and 32 segment terminals to drive up to 320224 pixels. ? internal step-up converter to guarantee functionality and contrast control irrespective of v dd . this converter can be deactivated, in which case the v lcd pin is used to provide the voltage to the lcd ? supports static, 1/2, 1/3, 1/4 and 1/8 duty ? supports static, 1/2, 1/3 and 1/4 bias ? phase inversion to reduce power consumption and emi ? up to 8 pixels can be programmed to blink ? unneeded segments and common pins can be used as general i/o pins ? lcd ram can be updated at any time owing to a double-buffer ? the lcd controller can operate in stop mode functional overview stm32l100rc 24/105 docid024995 rev 3 3.10 adc (analog-to-digital converter) a 12-bit analog-to-digital converters is embedded into stm32l100rc device with up to 20 external channels, performing conversions in single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs with up to 20 external channels in a group. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start triggers, to allow the application to synchronize a/d conversions and timers. an injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. the adc includes a specific low-power mode. the converter is able to operate at maximum speed even if the cpu is operating at a very low frequency and has an auto-shutdown function. the adc?s runtime and analog front-end current consumption are thus minimized whatever the mcu operating mode. 3.10.1 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc_in17 input channel. it enables accurate monitoring of the v dd value (when no external voltage, vref+, is available for adc). the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read- only mode. see table 14: embedded internal reference voltage calibration values . 3.11 dac (digital-to-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channels, independent or simultaneous conversions ? dma capability for each channel (including the underrun interrupt) ? external triggers for conversion ? input reference voltage v ref+ eight dac trigger inputs are used in the stm32l100rc. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. docid024995 rev 3 25/105 stm32l100rc 39 3.12 ultra-low-power comparators and reference voltage the stm32l100rc embeds two comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). ? one comparator with fixed threshold ? one comparator with rail-to-rail inputs, fast or slow mode. the threshold can be one of the following: ? dac output ? external i/o ? internal reference voltage (v refint ) or a sub-multiple (1/4, 1/2, 3/4) both comparators can wake up from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 a typical). 3.13 system configuration controller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. the highly flexible routing interface allows the application firmware to control the routing of different i/os to the tim2, tim3 and tim4 timer input captures. it also controls the routing of internal analog signals to adc1, comp1 and comp2 and the internal reference voltage v refint . 3.14 timers and watchdogs the ultra-low-power stm32l100rc device includes seven general-purpose timers, two basic timers, and two watchdog timers. table 5 compares the features of the general-purpose and basic timers. table 5. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2, tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim9 16-bit up, down, up/down any integer between 1 and 65536 no 2 no tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no functional overview stm32l100rc 26/105 docid024995 rev 3 3.14.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) there are seven synchronizable general-purpose timers embedded in the stm32l100rc device (see table 5 for differences). tim2, tim3, tim4 tim2, tim3, tim4 are based on 16-bit auto-reload up/down counter. they include a 16-bit prescaler. they feature four independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input captures/output compares/pwms on the largest packages. tim2, tim3, tim4 general-purpose timers can work together or with the tim10, tim11 and tim9 general-purpose timers via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4 all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim10, tim11 and tim9 tim10 and tim11 are based on a 16-bit auto-reload upcounter. tim9 is based on a 16-bit auto-reload up/down counter. they include a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4 full-featured general-purpose timers. they can also be used as simple time bases and be clocked by the lse clock source (32.768 khz) to provide time bases independent from the main cpu clock. 3.14.2 basic timers (tim6 and tim7) these timers are mainly used for dac trigger generation. they can also be used as generic 16-bit time bases. 3.14.3 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit downcounter with autoreload capability and a programmable clock source. it features a maskable system interrupt generation when the counter reaches 0. 3.14.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. docid024995 rev 3 27/105 stm32l100rc 39 3.14.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15 communication interfaces 3.15.1 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) the three usart interfaces are able to communicate at speeds of up to 4 mbit/s. they support irda sir endec and have lin master/slave capability. the three usarts provide hardware management of the cts and rts signals and are iso 7816 compliant. all usart interfaces can be served by the dma controller. 3.15.3 serial peripheral interface (spi) up to three spis are able to communicate at up to 16 mbits/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. the spis can be served by the dma controller. 3.15.4 universal serial bus (usb) the stm32l100rc embeds a usb device peripheral compatible with the usb full-speed 12 mbit/s. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and supports suspend/resume. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). 3.16 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of functional overview stm32l100rc 28/105 docid024995 rev 3 the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.17 development support 3.17.1 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag jtms and jtck pins are shared with swdat and swclk, respectively, and a specific sequence on the jtms pin is used to switch between jtag-dp and sw-dp. the jtag port can be permanently disabled with a jtag fuse. 3.17.2 embedded trace macrocell? the arm ? embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32l100rc through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. docid024995 rev 3 29/105 stm32l100rc 39 4 pin descriptions figure 3. stm32l100rc lqfp64 pinout 6 , # $ 0 # 7 + 5 0 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 0 ( / 3 # ? ) . 0 ( / 3 # ? / 5 4 . 2 3 4 0 # 0 # 0 # 0 # 6 3 3 ! 6 $ $ ! 0 ! 7 + 5 0 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 # 0 # 0 # 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 " 0 " 0 " 0 " 0 ! 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 " 0 " 6 3 3 ? 6 $ $ ? , 1 & 0 a i c pin descriptions stm32l100rc 30/105 docid024995 rev 3 table 6. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers docid024995 rev 3 31/105 stm32l100rc 39 table 7. stm32l100rc pin definitions pins pin name type (1) i / o level (2) main function (after reset) pin functions lqfp64 alternate functions additional functions 1v lcd sv lcd 2 pc13-wkup2 i/o ft pc13 wkup2/rtc_tamp1/ rtc_ts/rtc_out 3 pc14- osc32_in (3) i/o pc14 osc32_in 4 pc15- osc32_out (3) i/o pc15 osc32_out 5 ph0-osc_in (4) i ph0 osc_in 6 ph1- osc_out (4) o ph1 osc_out 7 nrst i/o nrst 8 pc0 i/o ft pc0 lcd_seg18 adc_in10/comp1_inp 9 pc1 i/o ft pc1 lcd_seg19 adc_in11/comp1_inp 10 pc2 i/o ft pc2 lcd_seg20 adc_in12/comp1_inp 11 pc3 i/o pc3 lcd_seg21 adc_in13/comp1_inp 12 v ssa sv ssa 13 v dda sv dda 14 pa0-wkup1 i/o ft pa0 tim2_ch1_etr/ usart2_cts wkup1/rtc_tamp2/ adc_in0/comp1_inp 15 pa1 i/o ft pa1 tim2_ch2/usart2_rts/ lcd_seg0 adc_in1/comp1_inp/ opamp1_vinp 16 pa2 i/o ft pa2 tim2_ch3/tim9_ch1/ usart2_tx/lcd_seg1 adc_in2/ comp1_inp/ opamp1_vinm 17 pa3 i/o pa3 tim2_ch4/tim9_ch2 /usart2_rx/lcd_seg2 adc_in3/ comp1_inp/opamp1_vout 18 v ss_4 sv ss_4 19 v dd_4 sv dd_4 20 pa4 i/o pa4 spi1_nss/spi3_nss/ i2s3_ws/usart2_ck adc_in4/dac_out1/ comp1_inp 21 pa5 i/o pa5 tim2_ch1_etr/spi1_sck adc_in5/ dac_out2/comp1_inp 22 pa6 i/o ft pa6 tim3_ch1/tim10_ch1/ spi1_miso/lcd_seg3 adc_in6/comp1_inp/ opamp2_vinp pin descriptions stm32l100rc 32/105 docid024995 rev 3 23 pa7 i/o ft pa7 tim3_ch2/tim11_ch1/ spi1_mosi/lcd_seg4 adc_in7/comp1_inp /opamp2_vinm 24 pc4 i/o ft pc4 lcd_seg22 adc_in14/comp1_inp 25 pc5 i/o ft pc5 lcd_seg23 adc_in15/comp1_inp 26 pb0 i/o pb0 tim3_ch3/lcd_seg5 adc_in8/comp1_inp/ opamp2_vout/vref_out 27 pb1 i/o ft pb1 tim3_ch4/lcd_seg6 adc_in9/ comp1_inp/vref_out 28 pb2 i/o ft pb2/boot1 boot1 comp1_inp 29 pb10 i/o ft pb10 tim2_ch3/i2c2_scl/ usart3_tx/lcd_seg10 30 pb11 i/o ft pb11 tim2_ch4/i2c2_sda/ usart3_rx/lcd_seg11 31 v ss_1 sv ss_1 32 v dd_1 sv dd_1 33 pb12 i/o ft pb12 tim10_ch1/i2c2_smba/ spi2_nss/i2s2_ws/ usart3_ck/lcd_seg12 adc_in18/comp1_inp 34 pb13 i/o ft pb13 tim9_ch1/spi2_sck/ i2s2_ck/ usart3_cts/ lcd_seg13 adc_in19/comp1_inp 35 pb14 i/o ft pb14 tim9_ch2/spi2_miso/ usart3_rts/lcd_seg14 adc_in20/comp1_inp 36 pb15 i/o ft pb15 tim11_ch1/spi2_mosi/ i2s2_sd/lcd_seg15 adc_in21/comp1_inp/ rtc_refin 37 pc6 i/o ft pc6 tim3_ch1/i2s2_mck/ lcd_seg24 38 pc7 i/o ft pc7 tim3_ch2/i2s3_mck/ lcd_seg25 39 pc8 i/o ft pc8 tim3_ch3/lcd_seg26 40 pc9 i/o ft pc9 tim3_ch4/lcd_seg27 41 pa8 i/o ft pa8 usart1_ck/mco/ lcd_com0 42 pa9 i/o ft pa9 usart1_tx/lcd_com1 table 7. stm32l100rc pin definitions (continued) pins pin name type (1) i / o level (2) main function (after reset) pin functions lqfp64 alternate functions additional functions docid024995 rev 3 33/105 stm32l100rc 39 43 pa10 i/o ft pa10 usart1_rx/lcd_com2 44 pa11 i/o ft pa11 usart1_cts/spi1_miso usb_dm 45 pa12 i/o ft pa12 usart1_rts/spi1_mosi usb_dp 46 pa13 i/o ft jtms- swdio jtms-swdio 47 v ss_2 sv ss_2 48 v dd_2 sv dd_2 49 pa14 i/o ft jtck- swclk jtck-swclk 50 pa15 i/o ft jtdi tim2_ch1_etr/spi1_nss/ spi3_nss/ i2s3_ws/lcd_seg17/jtdi 51 pc10 i/o ft pc10 spi3_sck/i2s3_ck/ usart3_tx/lcd_seg28/ lcd_seg40/lcd_com4 52 pc11 i/o ft pc11 spi3_miso/usart3_rx/ lcd_seg29 /lcd_seg41/lcd_com5 53 pc12 i/o ft pc12 spi3_mosi/i2s3_sd/ usart3_ck/lcd_seg30/ lcd_seg42/lcd_com6 54 pd2 i/o ft pd2 tim3_etr/lcd_seg31/ lcd_seg43/lcd_com7 55 pb3 i/o ft jtdo tim2_ch2/spi1_sck/ spi3_sck/i2s3_ck/ lcd_seg7/jtdo comp2_inm 56 pb4 i/o ft njtrst tim3_ch1/spi1_miso/ spi3_miso/lcd_seg8/ njtrst comp2_inp 57 pb5 i/o ft pb5 tim3_ch2/i2c1_smba/ spi1_mosi/spi3_mosi/ i2s3_sd/lcd_seg9 comp2_inp 58 pb6 i/o ft pb6 tim4_ch1/i2c1_scl/ usart1_tx comp2_inp 59 pb7 i/o ft pb7 tim4_ch2/i2c1_sda/ usart1_rx comp2_inp/pvd_in table 7. stm32l100rc pin definitions (continued) pins pin name type (1) i / o level (2) main function (after reset) pin functions lqfp64 alternate functions additional functions pin descriptions stm32l100rc 34/105 docid024995 rev 3 60 boot0 i boot0 61 pb8 i/o ft pb8 tim4_ch3/tim10_ch1/ i2c1_scl/lcd_seg16 62 pb9 i/o ft pb9 tim4_ch4/tim11_ch1/ i2c1_sda/lcd_com3 63 v ss_3 sv ss_3 64 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. the pc14 and pc15 i/os are only configured as osc32_in/osc32_out when the lse oscillator is on (by setting the lseon bit in the rcc_csr register). the lse oscillator pins osc32_in/osc32_out can be used as general-purpose ph0/ph1 i/os, respectively, when the lse oscillator is off (after reset, the lse oscillator is off). the lse has priority over the gpio function. for more details, refer to using the osc32_in/osc32_out pins as gpio pc14/pc15 port pins section in the stm32l100xx, stm32l151xx, stm32l152xx and stm32l162xx reference manual (rm0038). 4. the ph0 and ph1 i/os are only configured as osc_in/osc_out when the hse oscillator is on (by setting the hseon bit in the rcc_cr register). the hse oscillator pins osc_in/osc_out can be used as general-purpose ph0/ph1 i/os, respectively, when the hse oscillator is off ( after reset, the hse oscillator is off ). the hse has priority over the gpio function. table 7. stm32l100rc pin definitions (continued) pins pin name type (1) i / o level (2) main function (after reset) pin functions lqfp64 alternate functions additional functions stm32l100rc docid024995 rev 3 35/105 alternate functions table 8. alternate function input/output port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afio6 afio7 . . afio10 afio11 . . afio14 afio15 alternate function system tim2 tim3/4 tim9/ 10/11 i2c1/2 spi1/2 spi3 usart1/2/3 usb lcd cpri system boot0 boot0 event out nrst nrst pa0-wkup1 tim2_ch1_ etr usart2_cts timx_ic1 event out pa1 tim2_ch2 usart2_rts seg0 timx_ic2 event out pa2 tim2_ch3 tim9_ch1 usart2_tx seg1 timx_ic3 event out pa3 tim2_ch4 tim9_ch2 usart2_rx seg2 timx_ic4 event out pa4 spi1_nss spi3_nss i2s3_ws usart2_ck timx_ic1 event out pa5 tim2_ch1_etr spi1_sck timx_ic2 event out pa6 tim3_ch1 tim10_ ch1 spi1_miso seg3 timx_ic3 event out pa7 tim3_ch2 tim11_ ch1 spi1_mosi seg4 timx_ic4 event out pa8 mco usart1_ck com0 timx_ic1 event out pa9 usart1_tx com1 timx_ic2 event out pa10 usart1_rx com2 timx_ic3 event out pa11 spi1_miso usart1_cts usb_dm timx_ic4 event out pin descriptions stm32l100rc 36/105 docid024995 rev 3 pa12 spi1_mosi usart1_rts usb_dp timx_ic1 event out pa13 jtms-swdio timx_ic2 event out pa14 jtck-swclk timx_ic3 even tout pa15 jtdi tim2_ch1_etr spi1_nss spi3_nss i2s3_ws seg17 timx_ic4 even tout pb0 tim3_ch3 seg5 even tout pb1 tim3_ch4 seg6 event out pb2 boot1 event out pb3 jtdo tim2_ch2 spi1_sck spi3_sck i2s3_ck seg7 event out pb4 njtrst tim3_ch1 spi1_miso spi3_miso seg8 event out pb5 tim3_ch2 i2c1_ smba spi1_mosi spi3_mosi i2s3_sd seg9 event out pb6 tim4_ch1 i2c1_scl usart1_tx event out pb7 tim4_ch2 i2c1_sda usart1_rx event out pb8 tim4_ch3 tim10_ch1 i2c1_scl seg16 event out pb9 tim4_ch4 tim11_ch1 i2c1_sda com3 event out pb10 tim2_ch3 i2c2_scl usart3_tx seg10 event out table 8. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afio6 afio7 . . afio10 afio11 . . afio14 afio15 alternate function system tim2 tim3/4 tim9/ 10/11 i2c1/2 spi1/2 spi3 usart1/2/3 usb lcd cpri system stm32l100rc docid024995 rev 3 37/105 pb11 tim2_ch4 i2c2_sda usart3_rx seg11 event out pb12 tim10_ch1 i2c2_smba spi2_nss i2s2_ws usart3_ck seg12 event out pb13 tim9_ch1 spi2_sck i2s2_ck usart3_cts seg13 event out pb14 tim9_ch2 spi2_miso usart3_rts seg14 event out pb15 tim11_ch1 spi2_mosi i2s2_sd seg15 event out pc0 seg18 timx_ic1 event out pc1 seg19 timx_ic2 event out pc2 seg20 timx_ic3 event out pc3 seg21 timx_ic4 event out pc4 seg22 timx_ic1 event out pc5 seg23 timx_ic2 event out pc6 tim3_ch1 i2s2_mck seg24 timx_ic3 event out pc7 tim3_ch2 i2s3_mck seg25 timx_ic4 event out pc8 tim3_ch3 seg26 timx_ic1 event out pc9 tim3_ch4 seg27 timx_ic2 event out table 8. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afio6 afio7 . . afio10 afio11 . . afio14 afio15 alternate function system tim2 tim3/4 tim9/ 10/11 i2c1/2 spi1/2 spi3 usart1/2/3 usb lcd cpri system pin descriptions stm32l100rc 38/105 docid024995 rev 3 pc10 spi3_sck i2s3_ck usart3_tx com4/ seg28/ seg40 timx_ic3 event out pc11 spi3_miso usart3_rx com5/ seg29 /seg41 timx_ic4 event out pc12 spi3_mosi i2s3_sd usart3_ck com6/ seg30/ seg42 timx_ic1 event out pc13-wkup2 timx_ic2 event out pc14 osc32_in timx_ic3 event out pc15 osc32_out timx_ic4 event out pd2 tim3_etr com7/ seg31/ seg43 timx_ic3 event out ph0osc_in ph1osc_out table 8. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afio6 afio7 . . afio10 afio11 . . afio14 afio15 alternate function system tim2 tim3/4 tim9/ 10/11 i2c1/2 spi1/2 spi3 usart1/2/3 usb lcd cpri system docid024995 rev 3 39/105 stm32l100rc 39 5 memory mapping figure 4. memory map 0 6 9 & 5 & 7 , 0 5 h v h u y h g 7 , 0 7 , 0 5 7 & : : ' * , : ' * 6 3 , 8 6 $ 5 7 8 6 $ 5 7 6 < 6 & ) * 7 , 0 7 , 0 $ ' & 8 6 $ 5 7 6 3 , 6 3 , , & 3 : 5 7 , 0 , & ( ; 7 , 5 & & ) o d v k , q w h u i d f h ' 0 $ 8 6 % 5 h j l v w h u v e \ w h 8 6 % 7 , 0 7 , 0 / & ' [ [ [ [ & ' $ & [ 3 r u w $ 3 r u w % 3 r u w & 3 r u w ' 3 r u w + [ [ [ [ & [ [ & 2 0 3 5 , ' 0 $ [ ) ) [ [ [ [ & [ [ [ [ [ & [ [ [ [ [ [ [ [ & [ [ [ [ [ & [ [ [ [ [ & [ [ [ & [ [ [ [ & [ [ [ [ & [ [ & [ [ [ [ ) ) ) [ ) ) ) [ ) ) [ ) ) ) ) ) [ ) ) [ ) ) ) [ [ ) ) ) ) [ [ [ ) ) ) ) ) ) ) ) [ ( [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 1 r q y r o d w l o h p h p r u \ u h v h u y h g u h v h u y h g u h v h u y h g 6 \ v w h p p h p r u \ 2 s w l r q e \ w h ' d w d ( ( 3 5 2 0 u h v h u y h g ) o d v k p h p r u \ $ o l d v h g w r ) o d v k r u v \ v w h p p h p r u \ g h s h q g l q j r q % 2 2 7 s l q v u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g u h v h u y h g electrical characteristics stm32l100rc 40/105 docid024995 rev 3 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the device with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.6 v (for the 1.65 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the device have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 5 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 6 . figure 5. pin loading conditions figure 6. pin input voltage d l e & s ) 6 7 0 / [ [ s l q d l e 6 7 0 / [ [ s l q 9 , 1 docid024995 rev 3 41/105 stm32l100rc 96 6.1.6 power supply scheme figure 7. power supply scheme 0 6 9 $ q d o r j 2 6 & 3 / / & 2 0 3 ? 9 ' ' * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v 6 w d q g e \ s r z h u f l u f x l w u \ / 6 ( 5 7 & : d n h x s o r j l f 5 7 & e d f n x s u h j l v w h u v 1 ? q ) ? ? ) 5 h j x o d w r u 9 6 6 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ $ ' & ' $ & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 5 ( ) q ) ? ) 9 ' ' $ 1 q x p e h u r i 9 ' ' 9 6 6 s d l u v electrical characteristics stm32l100rc 42/105 docid024995 rev 3 6.1.7 optional lcd power supply scheme figure 8. optional lcd power supply scheme 1. option 1: lcd power supply is provided by a dedicated vlcd supply source, vsel switch is open. 2. option 2: lcd power supply is provided by the internal step-up converter, vsel switch is closed, an external capacitance is needed for correct behavior of this converter. 6.1.8 current consumption measurement figure 9. current consumption measurement scheme 0 6 9 9 ' ' 1 1 [ q ) [ ? ) 6 w h s x s & r q y h u w h u 9 6 6 1 9 ' ' q ) 9 / & ' 9 / & ' & ( ; 7 / & ' 9 6 ( / 2 s w l r q 2 s w l r q 1 [ q ) [ ? ) 1 [ 9 6 6 1 [ 9 ' ' 9 6 6 $ q ) ? ) $ 9 5 ( ) 9 5 ( ) 9 ' ' $ 9 / & ' 0 6 9 docid024995 rev 3 43/105 stm32l100rc 96 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 9: voltage characteristics , table 10: current characteristics , and table 11: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 9. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) ?0.3 4.0 v v in (2) input voltage on five-volt tolerant pin v ss ? 0.3 v dd +4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all different ground pins - 50 v ref+ ?v dda allowed voltage difference for v ref+ > v dda - 0.4 v v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. v in maximum must always be respected. refer to table 10 for maximum allowed injected current values. table 10. current characteristics symbol ratings max. unit i vdd( ) total current into sum of all v dd_x power lines (source) (1) 100 ma i vss( ) (2) total current out of sum of all v ss_x ground lines (sink) (1) 100 i vdd(pin) maximum current into each v dd_x power pin (source) (1) 70 i vss(pin) maximum current out of each vss_x ground pin (sink) (1) -70 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin - 25 i io(pin) total output current sunk by sum of all ios and control pins (2) 60 total output current sourced by sum of all ios and control pins (2) -60 i inj(pin) (3) injected current on five-volt tolerant i/o (4) , rst and b pins -5/+0 injected current on any other pin (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count lqfp packages. 3. negative injection disturbs the analog performance of the device. see note in section 6.3.17 . 4. positive current injection is not possible on these i/os. a negative injection is induced by v in docid024995 rev 3 45/105 stm32l100rc 96 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the conditions summarized in table 12 . 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up . 3. to sustain a voltage higher than vdd+0.3v, the internal pull-up/pull-down resistors must be disabled 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 63: thermal characteristics on page 101 ). 5. in low-power dissipation state, t a can be extended to -40c to 105c temperature range as long as t j does not exceed t j max (see table 63: thermal characteristics on page 101 ). table 13. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd (1) v dd rise time rate bor detector enabled 0 - s/v bor detector disabled 0 - 1000 v dd fall time rate bor detector enabled 20 - bor detector disabled 0 - 1000 t rsttempo (1) reset temporization v dd rising, bor enabled - 2 3.3 ms v dd rising, bor disabled (2) 0.4 0.7 1.6 v por/pdr power on/power down reset threshold falling edge 1 1.5 1.65 v rising edge 1.3 1.5 1.65 v bor0 brown-out reset threshold 0 falling edge 1.67 1.7 1.74 rising edge 1.69 1.76 1.8 v bor1 brown-out reset threshold 1 falling edge 1.87 1.93 1.97 rising edge 1.96 2.03 2.07 v bor2 brown-out reset threshold 2 falling edge 2.22 2.30 2.35 rising edge 2.31 2.41 2.44 electrical characteristics stm32l100rc 46/105 docid024995 rev 3 v bor3 brown-out reset threshold 3 falling edge 2.45 2.55 2.6 v rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 falling edge 2.68 2.8 2.85 rising edge 2.78 2.9 2.95 v pvd0 programmable voltage detector threshold 0 falling edge 1.8 1.85 1.88 rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.20 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 v hyst hysteresis voltage bor0 threshold - 40 - mv all bor and pvd thresholds excepting bor0 - 100 - 1. guaranteed by characterization results, not tested in production. 2. valid for device version without bor at power up. please see option ?d? in ordering information scheme for more details. table 13. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit docid024995 rev 3 47/105 stm32l100rc 96 6.3.3 embedded internal reference voltage the parameters given in table 15 are based on characterization results, unless otherwise specified. table 14. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c 5 c v dda = 3 v 10 mv 0x1ff8 00f8 - 0x1ff8 00f9 table 15. embedded internal reference voltage symbol parameter conditions min typ max unit v refint out (1) internal reference voltage ? 40 c < t j < +110 c 1.202 1.224 1.242 v i refint internal reference current consumption - - 1.4 2.3 a t vrefint internal reference startup time - - 2 3 ms v vref_meas v dda and v ref+ voltage during v refint factory measure - 2.99 3 3.01 v a vref_meas accuracy of factory-measured v ref value (2) including uncertainties due to adc and v dda /v ref+ values - - 5 mv t coeff (3) temperature coefficient ?40 c < t j < +110 c - 20 50 ppm/ c 0 c < t j < +50 c - - 20 a coeff (3) long-term stability 1000 hours, t= 25 c - - 1000 ppm v ddcoeff (3) voltage coefficient 3.0 v < v dda < 3.6 v - - 2000 ppm/v t s_vrefint (3) adc sampling time when reading the internal reference voltage -4-- s t adc_buf (3) startup time of reference voltage buffer for adc ---10 s i buf_adc (3) consumption of reference voltage buffer for adc - - 13.5 25 a i vref_out (3) vref_out output current (4) ---1 a c vref_out (3) vref_out output load - - - 50 pf i lpbuf (3) consumption of reference voltage buffer for vref_out and comp - - 730 1200 na v refint_div1 (3) 1/4 reference voltage - 24 25 26 % v refin t v refint_div2 (3) 1/2 reference voltage - 49 50 51 v refint_div3 (3) 3/4 reference voltage - 74 75 76 1. guaranteed by test in production. 2. the internal v ref value is individually measured in production and stored in dedicated eeprom bytes. 3. guaranteed by design, not tested in production. 4. to guarantee less than 1% vref_out deviation. electrical characteristics stm32l100rc 48/105 docid024995 rev 3 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 9: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to the dhrystone 2.1 code, unless otherwise specified. the current consumption values are derived from tests performed under ambient temperature t a = 25 c and v dd supply voltage conditions summarized in table 12: general operating conditions , unless otherwise specified. the mcu is placed under the following conditions: ? all i/o pins are configured in analog input mode ? all peripherals are disabled except when explicitly mentioned. ? the flash memory access time, 64-bit access and prefetch is adjusted depending on f hclk frequency and voltage range to provide the best cpu performance. ? when the peripherals are enabled f apb1 = f apb2 = f ahb . ? when pll is on, the pll inputs are equal to hsi = 16 mhz (if internal clock is used) or hse = 16 mhz (if hse bypass mode is used). ? the hse user clock applied to osci_in input follows the characteristic specified in table 25: high-speed external user clock characteristics . ? for maximum current consumption v dd = v dda = 3.6 v is applied to all supply pins. ? for typical current consumption v dd = v dda = 3.0 v is applied to all supply pins if not specified otherwise. docid024995 rev 3 49/105 stm32l100rc 96 table 16. current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ max (1) unit i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 215 400 a 2 mhz 400 600 4 mhz 725 960 range 2, v core =1.5 v vos[1:0] = 10 4 mhz 0.915 1.1 ma 8 mhz 1.75 2.1 16 mhz 3.4 3.9 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 2.1 2.8 16 mhz 4.2 4.9 32 mhz 8.25 9.4 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 3.5 4 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 8.2 9.6 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] = 11 65 khz 40.5 110 a msi clock, 524 khz 524 khz 125 190 msi clock, 4.2 mhz 4.2 mhz 775 900 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). electrical characteristics stm32l100rc 50/105 docid024995 rev 3 table 17. current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk typ max (1) unit i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse =f hclk up to 16 mhz, included f hse =f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] =11 1 mhz 185 240 a 2 mhz 345 410 4 mhz 645 880 (3) range 2, v core =1.5 v vos[1:0] =10 4 mhz 0.755 1.4 ma 8 mhz 1.5 2.1 16 mhz 3 3.5 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 1.8 2.8 16 mhz 3.6 4.1 32 mhz 7.15 8.3 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] =10 16 mhz 2.95 3.5 range 1, v core =1.8 v vos[1:0] =01 32 mhz 7.15 8.4 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] =11 65 khz 38.5 85 a msi clock, 524 khz 524 khz 110 160 msi clock, 4.2 mhz 4.2 mhz 690 810 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. oscillator bypassed (hseby p=1in rcc_cr register). 3. guaranteed by test in production. docid024995 rev 3 51/105 stm32l100rc 96 table 18. current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit i dd (sleep) supply current in sleep mode, flash on f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 60.5 130 a 2 mhz 89.5 195 4 mhz 150 310 range 2, v core =1.5 v vos[1:0] = 10 4 mhz 180 310 8 mhz 320 440 16 mhz 605 830 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 380 550 16 mhz 695 990 32 mhz 1600 2100 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 650 890 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 1600 2200 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] = 11 65 khz 30 60 msi clock, 524 khz 524 khz 44 99 msi clock, 4.2 mhz 4.2 mhz 155 210 supply current in sleep mode, flash off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 50 130 2 mhz 78.5 190 4 mhz 140 320 range 2, v core =1.5 v vos[1:0] = 10 4 mhz 165 320 8 mhz 310 460 16 mhz 590 840 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 350 540 16 mhz 680 1000 32 mhz 1600 2100 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 640 910 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 1600 2200 supply current in sleep mode, flash on msi clock, 65 khz range 3, v core =1.2v vos[1:0] = 11 65 khz 19 90 msi clock, 524 khz 524 khz 33 96 msi clock, 4.2 mhz 4.2 mhz 145 220 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register) electrical characteristics stm32l100rc 52/105 docid024995 rev 3 table 19. current consumption in low-power run mode symbol parameter conditions typ max (1) unit i dd (lp run) supply current in low-power run mode all peripherals off, code executed from ram, flash switched off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 8.6 12 a t a = 85 c 19 25 t a = 105 c 35 47 msi clock, 65 khz f hclk = 65 khz t a =-40 c to 25 c 14 16 t a = 85 c 24 29 t a = 105 c 40 51 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 26 29 t a = 55 c 28 31 t a = 85 c 36 42 t a = 105 c 52 64 all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 20 24 t a = 85 c 32 37 t a = 105 c 49 61 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 26 30 t a = 85 c 38 44 t a = 105 c 55 67 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 41 46 t a = 55 c 44 50 t a = 85 c 56 87 t a = 105 c 73 110 i dd max (lp run) max allowed current in low-power run mode v dd from 1.65 v to 3.6 v - 200 1. guaranteed by characterization results, not tested in production, unless otherwise specified. docid024995 rev 3 53/105 stm32l100rc 96 table 20. current consumption in low-power sleep mode symbol parameter conditions typ max (1) unit i dd (lp sleep) supply current in low-power sleep mode all peripherals off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz flash off t a = -40 c to 25 c 4.4 - a msi clock, 65 khz f hclk = 32 khz flash on t a = -40 c to 25 c 14 16 t a = 85 c 19 23 t a = 105 c 27 33 msi clock, 65 khz f hclk = 65 khz, flash on t a = -40 c to 25 c 15 17 t a = 85 c 20 23 t a = 105 c 28 33 msi clock, 131 khz f hclk = 131 khz, flash on t a = -40 c to 25 c 17 19 t a = 55 c 18 21 t a = 85 c 22 25 t a = 105 c 30 35 tim9 and usart1 enabled, flash on, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 14 16 t a = 85 c 19 22 t a = 105 c 27 32 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 15 17 t a = 85 c 20 23 t a = 105 c 28 33 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 17 19 t a = 55 c 18 21 t a = 85 c 22 25 t a = 105 c 30 36 i dd max (lp sleep) max allowed current in low-power sleep mode v dd from 1.65 v to 3.6 v - 200 1. guaranteed by characterization results, not tested in production, unless otherwise specified. electrical characteristics stm32l100rc 54/105 docid024995 rev 3 table 21. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) unit i dd (stop with rtc) supply current in stop mode with rtc enabled rtc clocked by lsi or lse external clock (32.768khz), regulator in lp mode, hsi and hse off (no independent watchdog) lcd off t a = -40c to 25c v dd = 1.8 v 1.15 - a t a = -40c to 25c 1.4 - t a = 55c 2 - t a = 85c 3.4 10 t a = 105c 6.35 23 lcd on (static duty) (2) t a = -40c to 25c 1.55 6 t a = 55c 2.15 7 t a = 85c 3.55 12 t a = 105c 6.3 27 lcd on (1/8 duty) (3) t a = -40c to 25c 3.9 10 t a = 55c 4.65 11 t a = 85c 6.25 16 t a = 105c 9.1 44 rtc clocked by lse external quartz (32.768khz), regulator in lp mode, hsi and hse off (no independent watchdog (4) lcd off t a = -40c to 25c 1.5 - t a = 55c 2.15 - t a = 85c 3.7 - t a = 105c 6.75 - lcd on (static duty) (2) t a = -40c to 25c 1.6 - t a = 55c 2.3 - t a = 85c 3.8 - t a = 105c 6.85 - lcd on (1/8 duty) (3) t a = -40c to 25c 4 - t a = 55c 4.85 - t a = 85c 6.5 - t a = 105c 9.1 - lcd off t a = -40c to 25c v dd = 1.8v 1.2 - t a = -40c to 25c v dd = 3.0v 1.5 - t a = -40c to 25c v dd = 3.6v 1.75 - docid024995 rev 3 55/105 stm32l100rc 96 i dd (stop) supply current in stop mode (rtc disabled) regulator in lp mode, hsi and hse off, independent watchdog and lsi enabled t a = -40c to 25c 1.8 2.2 a regulator in lp mode, lsi, hsi and hse off (no independent watchdog) t a = -40c to 25c 0.435 1 t a = 55c 0.99 3 t a = 85c 2.4 9 t a = 105c 5.5 22 (5) i dd (wu from stop) supply current during wakeup from stop mode msi = 4.2 mhz t a = -40c to 25c 2- ma msi = 1.05 mhz 1.45 - msi = 65 khz (6) 1.45 - 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. lcd enabled with external vlcd, static duty, division ratio = 256, all pixels active, no lcd connected. 3. lcd enabled with external vlcd, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no lcd connected. 4. based on characterization done with a 32.768 khz crystal (mc306-g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading capacitors. 5. guaranteed by test in production. 6. when msi = 64 khz, the rms current is measured over the first 15 s following the wakeup event. for the remaining part of the wakeup period, the current corresponds the run mode current. table 21. typical and maximum current consumptions in stop mode (continued) symbol parameter conditions typ max (1) unit electrical characteristics stm32l100rc 56/105 docid024995 rev 3 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in the following table. the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on table 22. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit i dd (standby with rtc) supply current in standby mode with rtc enabled rtc clocked by lsi (no independent watchdog) t a = -40 c to 25 c v dd = 1.8 v 0.905 - a t a = -40 c to 25 c 1.15 1.9 t a = 55 c 1.5 2.2 t a = 85 c 1.75 4 t a = 105 c 2.1 8.3 (2) rtc clocked by lse external quartz (no independent watchdog) (3) t a = -40 c to 25 c v dd = 1.8 v 0.98 - t a = -40 c to 25 c 1.3 - t a = 55 c 1.7 - t a = 85 c 2.05 - t a = 105 c 2.45 - i dd (standby) supply current in standby mode (rtc disabled) independent watchdog and lsi enabled t a = -40 c to 25 c 1 1.7 independent watchdog and lsi off t a = -40 c to 25 c 0.29 0.6 t a = 55 c 0.345 0.9 t a = 85 c 0.575 2.75 t a = 105 c 1.45 7 (2) i dd (wu from standby) supply current during wakeup time from standby mode t a = -40 c to 25 c 1 - ma 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. guaranteed by test in production. 3. based on characterization done with a 32.768 khz crystal (mc306-g-06q-32.768, manufacturer jfvny) with two 6.8pf loading capacitors. docid024995 rev 3 57/105 stm32l100rc 96 table 23. peripheral current consumption (1) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core = 1.8 v vos[1:0] = 01 range 2, v core = 1.5 v vos[1:0] = 10 range 3, v core = 1.2 v vos[1:0] = 11 low-power sleep and run apb1 tim2 11.2 8.9 7.0 8.9 a/mhz (f hclk ) tim3 11.2 9.0 7.1 9.0 tim4 12.9 10.4 8.2 10.4 tim5 14.4 11.5 9.0 11.5 tim6 4.0 3.1 2.4 3.1 tim7 3.8 3.0 2.3 3.0 lcd 5.8 4.6 3.6 4.6 wwdg 2.9 2.3 1.8 2.3 spi2 6.5 5.2 4.1 5.2 spi3 5.9 4.6 3.6 4.6 usart2 8.8 7.0 5.5 7.0 usart3 8.4 6.8 5.3 6.8 i2c1 7.3 5.8 4.6 5.8 i2c2 7.9 6.3 5.0 6.3 usb 13.3 10.6 8.3 10.6 pwr 2.8 2.2 1.8 2.2 dac 6.1 4.9 3.9 4.9 comp 4.8 3.8 3.0 3.8 electrical characteristics stm32l100rc 58/105 docid024995 rev 3 apb2 syscfg & ri 2.6 2.0 1.6 2.0 a/mhz (f hclk ) tim9 7.9 6.4 5.0 6.4 tim10 5.9 4.7 3.8 4.7 tim11 5.9 4.6 3.7 4.6 adc (2) 10.5 8.3 6.6 8.3 spi1 4.3 3.4 2.8 3.4 usart1 8.8 7.1 5.6 7.1 ahb gpioa 4.3 3.3 2.6 3.3 gpiob 4.3 3.5 2.8 3.5 gpioc 4.0 3.2 2.5 3.2 gpiod 4.1 3.3 2.5 3.3 gpioe 4.2 3.4 2.7 3.4 gpioh 3.7 3.0 2.3 3.0 crc 0.8 0.6 0.5 0.6 flash 11.1 9.4 8 - (3) dma1 15.6 12.7 10 12.7 dma2 16.3 13.4 10.5 13.4 all enabled 187 154 120 144.6 i dd (rtc) 0.4 a i dd (lcd) 3.1 i dd (adc) (4) 1450 i dd (dac) (5) 340 i dd (comp1) 0.16 i dd (comp2) slow mode 2 fast mode 5 i dd (pvd / bor) (6) 2.6 i dd (iwdg) 0.25 1. data based on differential i dd measurement between all peripherals off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz (range 1), f hclk = 16 mhz (range 2), f hclk = 4 mhz (range 3), f hclk = 64khz (low-power run/sleep), f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in both cases. no i/o pins toggling. not tested in production. 2. hsi oscillator is off for this measure. table 23. peripheral current consumption (1) (continued) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core = 1.8 v vos[1:0] = 01 range 2, v core = 1.5 v vos[1:0] = 10 range 3, v core = 1.2 v vos[1:0] = 11 low-power sleep and run docid024995 rev 3 59/105 stm32l100rc 96 6.3.5 wakeup time from low-power mode the wakeup times given in the following table are measured with the msi rc oscillator. the clock source used to wake up the device depends on the current operating mode: ? sleep mode: the clock source is the clock that was set before entering sleep mode ? stop mode: the clock source is the msi oscillator in the range configured before entering stop mode ? standby mode: the clock source is the msi oscillator running at 2.1 mhz all timings are derived from tests performed under the conditions summarized in table 12 . 3. in low-power sleep and run mode, the flash memory must always be in power-down mode. 4. data based on a differential i dd measurement between adc in reset configuration and continuous adc conversion (hsi consumption not included). 5. data based on a differential i dd measurement between dac in reset configuration and continuous dac conversion of v dd /2. dac is in buffered mode, output is left floating. 6. including supply current of internal reference voltage. table 24. low-power mode wakeup timings symbol parameter conditions typ max (1) 1. guaranteed by characterization, not tested in production, unless otherwise specified unit t wusleep wakeup from sleep mode f hclk = 32 mhz 0.4 - s t wusleep_lp wakeup from low-power sleep mode, f hclk = 262 khz f hclk = 262 khz flash enabled 46 - f hclk = 262 khz flash switched off 46 - t wustop wakeup from stop mode, regulator in run mode ulp bit = 1 and fwu bit = 1 f hclk = f msi = 4.2 mhz 8.2 - wakeup from stop mode, regulator in low-power mode ulp bit = 1 and fwu bit = 1 f hclk = f msi = 4.2 mhz voltage range 1 and 2 7.7 8.9 f hclk = f msi = 4.2 mhz voltage range 3 8.2 13.1 f hclk = f msi = 2.1 mhz 10.2 13.4 f hclk = f msi = 1.05 mhz 16 20 f hclk = f msi = 524 khz 31 37 f hclk = f msi = 262 khz 57 66 f hclk = f msi = 131 khz 112 123 f hclk = msi = 65 khz 221 236 t wustdby wakeup from standby mode ulp bit = 1 and fwu bit = 1 f hclk = msi = 2.1 mhz 58 104 wakeup from standby mode fwu bit = 0 f hclk = msi = 2.1 mhz 2.6 3.25 ms electrical characteristics stm32l100rc 60/105 docid024995 rev 3 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio.the external clock signal has to respect the i/o characteristics in section 6.3.12 . however, the recommended clock input waveform is shown in figure 10 . figure 10. high-speed external clock source ac timing diagram table 25. high-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f hse_ext user external clock source frequency css is on or pll is used 1 8 32 mhz css is off, pll not used 0 8 32 mhz v hseh osc_in input pin high level voltage - 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss - 0.3v dd t w(hseh) t w(hsel) osc_in high or low time 12 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 c in(hse) osc_in input capacitance - 2.6 - pf 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid024995 rev 3 61/105 stm32l100rc 96 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under the conditions summarized in table 12 . figure 11. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 1 to 24 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on characterization results obtained with typical external components specified in table 27 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 26. low-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - 1 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss - 0.3v dd t w(lseh) t w(lsel) osc32_in high or low time 465 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 10 c in(lse) osc32_in input capacitance - - 0.6 - pf 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics stm32l100rc 62/105 docid024995 rev 3 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 12 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 27. hse oscillator characteristics (1)(2) symbol parameter conditions min typ max unit f osc_in oscillator frequency - 1 24 mhz r f feedback resistor - - 200 - k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) r s = 30 -20 - pf i hse hse driving current v dd = 3.3 v, v in = v ss with 30 pf load -- 3 ma i dd(hse) hse oscillator power consumption c = 20 pf f osc = 16 mhz -- 2.5 (startup) 0.7 (stabilized) ma c = 10 pf f osc = 16 mhz -- 2.5 (startup) 0.46 (stabilized) g m oscillator transconductance startup 3.5 - - ma /v t su(hse) (4) startup time v dd is stabilized - 1 - ms 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. guaranteed by characterization results, not tested in production. 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. docid024995 rev 3 63/105 stm32l100rc 96 figure 12. hse oscillator circuit diagram 1. r ext value depends on the crystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on characterization results obtained with typical external components specified in table 28 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 28. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by characterization results, not tested in production. symbol parameter conditions min typ max unit f lse low speed external oscillator frequency - - 32.768 - khz r f feedback resistor - - 1.2 - m c (2) 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details. r s = 30 k -8 -pf i lse lse driving current v dd = 3.3 v, v in = v ss - - 1.1 a i dd (lse) lse oscillator current consumption v dd = 1.8 v - 450 - na v dd = 3.0 v - 600 - v dd = 3.6v - 750 - g m oscillator transconductance - 3 - - a/v t su(lse) (4) startup time v dd is stabilized - 1 - s 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( w r f r u h & / & / 5 ) 6 7 0 5 h v r q d w r u & r q v x p s w l r q f r q w u r o j p 5 p & p / p & 2 5 h v r q d w r u d l e electrical characteristics stm32l100rc 64/105 docid024995 rev 3 note: for c l1 and c l2 , it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 13 ). c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 13. typical application with a 32.768 khz crystal 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. d l e 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / 5 ) 6 7 0 / [ [ n + ] u h v r q d w r u & / 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q docid024995 rev 3 65/105 stm32l100rc 96 6.3.7 internal clock source characteristics the parameters given in table 29 are derived from tests performed under the conditions summarized in table 12 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator table 29. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency v dd = 3.0 v - 16 - mhz trim (1)(2) 1. the trimming step differs depending on the trimming code. it is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). hsi user-trimmed resolution trimming code is not a multiple of 16 - 0.4 0.7 % trimming code is a multiple of 16 - - 1.5 % acc hsi (2) 2. guaranteed by characterization results, not tested in production. accuracy of the factory-calibrated hsi oscillator v dda = 3.0 v, t a = 25 c -1 (3) 3. guaranteed by test in production. -1 (3) % v dda = 3.0 v, t a = 0 to 55 c -1.5 - 1.5 % v dda = 3.0 v, t a = -10 to 70 c -2 - 2 % v dda = 3.0 v, t a = -10 to 85 c -2.5 - 2 % v dda = 3.0 v, t a = -10 to 105 c -4 - 2 % v dda = 1.65 v to 3.6 v t a = -40 to 105 c -4 - 3 % t su(hsi) (2) hsi oscillator startup time - - 3.7 6 s i dd(hsi) (2) hsi oscillator power consumption - - 100 140 a table 30. lsi oscillator characteristics symbol parameter min typ max unit f lsi (1) 1. guaranteed by test in production. lsi frequency 26 38 56 khz d lsi (2) 2. this is a deviation for an individual part, once the initial frequency has been measured. lsi oscillator frequency drift 0c t a 105c -10 - 4 % t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - - 200 s i dd(lsi) (3) lsi oscillator power consumption - 400 510 na electrical characteristics stm32l100rc 66/105 docid024995 rev 3 multi-speed internal (msi) rc oscillator table 31. msi oscillator characteristics symbol parameter condition typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 65.5 - khz msi range 1 131 - msi range 2 262 - msi range 3 524 - msi range 4 1.05 - mhz msi range 5 2.1 - msi range 6 4.2 - acc msi frequency error after factory calibration - 0.5 - % d temp(msi) (1) msi oscillator frequency drift 0 c t a 105 c - 3-% d volt(msi) (1) msi oscillator frequency drift 1.65 v v dd 3.6 v, t a = 25 c - - 2.5 %/v i dd(msi) (2) msi oscillator power consumption msi range 0 0.75 - a msi range 1 1 - msi range 2 1.5 - msi range 3 2.5 - msi range 4 4.5 - msi range 5 8 - msi range 6 15 - t su(msi) msi oscillator startup time msi range 0 30 - s msi range 1 20 - msi range 2 15 - msi range 3 10 - msi range 4 6 - msi range 5 5 - msi range 6, voltage range 1 and 2 3.5 - msi range 6, voltage range 3 5- docid024995 rev 3 67/105 stm32l100rc 96 t stab(msi) (2) msi oscillator stabilization time msi range 0 - 40 s msi range 1 - 20 msi range 2 - 10 msi range 3 - 4 msi range 4 - 2.5 msi range 5 - 2 msi range 6, voltage range 1 and 2 -2 msi range 3, voltage range 3 -3 f over(msi) msi oscillator frequency overshoot any range to range 5 -4 mhz any range to range 6 -6 1. this is a deviation for an individual part, once the initial frequency has been measured. 2. guaranteed by characterization results, not tested in production. table 31. msi oscillator characteristics (continued) symbol parameter condition typ max unit electrical characteristics stm32l100rc 68/105 docid024995 rev 3 6.3.8 pll characteristics the parameters given in table 32 are derived from tests performed under the conditions summarized in table 12 . 6.3.9 memory characteristics the characteristics are given at t a = -40 to 105 c unless otherwise specified. ram memory table 32. pll characteristics symbol parameter value unit min typ max (1) 1. guaranteed by characterization results, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 2 - 24 mhz pll input clock duty cycle 45 - 55 % f pll_out pll output clock 2 - 32 mhz t lock pll lock time pll input = 16 mhz pll vco = 96 mhz - 115 160 s jitter cycle-to-cycle jitter - - 600 ps i dda (pll) current consumption on v dda - 220 450 a i dd (pll) current consumption on v dd - 120 150 table 33. ram and hardware registers symbol parameter conditions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). stop mode (or reset) 1.65 - - v docid024995 rev 3 69/105 stm32l100rc 96 flash memory and data eeprom table 34. flash memory and data eeprom characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit v dd operating voltage read / write / erase - 1.65 - 3.6 v t prog programming/ erasing time for byte / word / double word / half-page erasing - 3.28 3.94 ms programming - 3.28 3.94 i dd average current during the whole programming / erase operation t a = 25 c, v dd = 3.6 v - 600 a maximum current (peak) during the whole programming / erase operation - 1.5 2.5 ma table 35. flash memory and data eeprom endurance and retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization results, not tested in production. typ max n cyc (2) cycling (erase / write) program memory t a = -40c to 105 c 10 -- kcycles cycling (erase / write) eeprom data memory 300 -- t ret (2) 2. characterization is done according to jedec jesd22-a117. data retention (program memory) after 10 kcycles at t a = 85 c t ret = +85 c 30 - - years data retention (eeprom data memory) after 300 kcycles at t a = 85 c 30 - - data retention (program memory) after 10 kcycles at t a = 105 c t ret = +105 c 10 - - data retention (eeprom data memory) after 300 kcycles at t a = 105 c 10 - - electrical characteristics stm32l100rc 70/105 docid024995 rev 3 6.3.10 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 36 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. table 36. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, , t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, , t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-4 4a docid024995 rev 3 71/105 stm32l100rc 96 to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.11 electrical sensitivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 37. emi characteristics symbol parameter conditions monitored frequency band max vs. frequency range unit 4 mhz voltage range 3 16 mhz voltage range 2 32 mhz voltage range 1 s emi peak level v dd = v, t a = 25 c, package compliant with iec 61967-2 0.1 to 30 mhz 3 -6 -5 db v 30 to 130 mhz 18 4 -7 130 mhz to 1ghz 15 5 -7 sae emi level 2.5 2 1 - table 38. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1. ii 500 v electrical characteristics stm32l100rc 72/105 docid024995 rev 3 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.12 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failure (for example reset occurrence oscillator frequency deviation, lcd levels). the test results are given in the table 40 . table 39. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 40. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on all 5 v tolerant (ft) pins -5 (1) 1. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. na ma injected current on boot0 -0 na injected current on any other pin -5 (1) +5 docid024995 rev 3 73/105 stm32l100rc 96 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 47 are derived from tests performed under the conditions summarized in table 12 . all i/os are cmos and ttl compliant. table 41. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage tc and ft i/o - - 0.3 v dd (1)(2) v boot0 - - 0.14 v dd (2) v ih input high level voltage tc i/o 0.45 v dd +0.38 (2) -- ft i/o 0.39 v dd +0.59 (2) -- boot0 0.15 v dd +0.56 (2) -- v hys i/o schmitt trigger voltage hysteresis (2) tc and ft i/o - 10% v dd (3) - boot0 - 0.01 - i lkg input leakage current (4) v ss v in v dd i/os with lcd - - 50 na v ss v in v dd i/os with analog switches - - 50 v ss v in v dd i/os with analog switches and lcd - - 50 v ss v in v dd i/os with usb - - 250 v ss v in v dd tc and ft i/os - - 50 ft i/o v dd v in 5v - - 10 a r pu weak pull-up equivalent resistor (5)(1) v in = v ss 30 45 60 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 45 60 k c io i/o pin capacitance - - 5 - pf 1. guaranteed by test in production 2. guaranteed by design, not tested in production. 3. with a minimum of 200 mv. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order). electrical characteristics stm32l100rc 74/105 docid024995 rev 3 output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma with the non-standard v ol /v oh specifications given in table 42 . in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd( ) (see table 10 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss( ) (see table 10 ). output voltage levels unless otherwise specified, the parameters given in table 42 are derived from tests performed under the conditions summarized in table 12 . all i/os are cmos and ttl compliant. table 42. output voltage characteristics symbol parameter conditions min max unit v ol (1)(2) 1. the i io current sunk by the device must always respect the absolute maximum rating specified in table 10 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. guaranteed by test in production. output low level voltage for an i/o pin i io = 8 ma 2.7 v < v dd < 3.6 v - 0.4 v v oh (2)(3) 3. the i io current sourced by the device must always respect the absolute maximum rating specified in table 10 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd -0.4 - v ol (3)(4) output low level voltage for an i/o pin i io = 4 ma 1.65 v < v dd < 3.6 v - 0.45 v oh (3)(4) output high level voltage for an i/o pin v dd -0.45 - v ol (1)(4) 4. guaranteed by characterization results, not tested in production. output low level voltage for an i/o pin i io = 20 ma 2.7 v < v dd < 3.6 v - 1.3 v oh (3)(4) output high level voltage for an i/o pin v dd -1.3 - docid024995 rev 3 75/105 stm32l100rc 96 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 14 and table 43 , respectively. unless otherwise specified, the parameters given in table 43 are derived from tests performed under the conditions summarized in table 12 . table 43. i/o ac characteristics (1) ospeedrx [1:0] bit value (1) symbol parameter conditions min max (2) unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v - 400 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 625 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 625 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v-2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 1 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 125 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 250 10 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v-10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 2 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v-25 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 125 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd = 2.7 v to 3.6 v-50 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 8 t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v-5 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 30 -t extipw pulse width of external signals detected by the exti controller -8- 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32l151xx, stm32l152xx and stm32l162xx reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. 3. the maximum frequency is defined in figure 14 . electrical characteristics stm32l100rc 76/105 docid024995 rev 3 figure 14. i/o ac characteristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 44 ) unless otherwise specified, the parameters given in table 44 are derived from tests performed under the conditions summarized in table 12 . a i c t r ) / o u t / 5 4 0 5 4 % 8 4 % 2 . ! , / . p & - a x i m u m f r e q u e n c y i s a c h i e v e d i f t r t f ? 4 a n d i f t h e d u t y c y c l e i s w h e n l o a d e d b y p & 4 t f ) / o u t table 44. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - - 0.3 v dd v v ih(nrst) (1) nrst input high level voltage - 0.39v dd +0.59 - - v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v -- 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v -- v hys(nrst) (1) nrst schmitt trigger voltage hysteresis - - 10%v dd (2) -mv r pu weak pull-up equivalent resistor (3) v in = v ss 30 45 60 k v f(nrst) (1) nrst input filtered pulse ---50ns v nf(nrst) (3) nrst input not filtered pulse - 350 - - ns 1. guaranteed by design, not tested in production. 2. with a minimum of 200 mv. 3. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is around 10%. docid024995 rev 3 77/105 stm32l100rc 96 figure 15. recommended nrst pin protection 1. the reset network protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 44 . otherwise the reset will not be taken into account by the device. 6.3.15 tim timer characteristics the parameters given in the table 45 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output ction characteristics (output compare, input capture, external clock, pwm output). d l e 6 7 0 / [ [ 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o u h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 45. timx (1) characteristics 1. timx is used as a general term to refer to the tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1-t timxclk f timxclk = 32 mhz 31.25 - ns f ext timer external clock frequency on ch1 to ch4 0f timxclk /2 mhz f timxclk = 32 mhz 0 16 mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) - 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count - - 65536 65536 t timxclk f timxclk = 32 mhz - 134.2 s electrical characteristics stm32l100rc 78/105 docid024995 rev 3 6.3.16 communications interfaces i 2 c interface characteristics the device i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: sda and scl are not ?true? open-drain i/o pins. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 46 . refer also to section 6.3.13: i/o port characteristics for more details on the input/output ction characteristics (sda and scl) . table 46. i 2 c characteristics symbol parameter standard mode i 2 c (1) (2) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i2c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time - 3450 (3) - 900 (3) 3. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes that are suppressed by the analog filter 050 (4) 4. the minimum width of the spikes filtered by the analog filter is above t sp(max) . 050 (4) ns docid024995 rev 3 79/105 stm32l100rc 96 figure 16. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. 4. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. table 47. scl frequency (f pclk1 = 32 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for speeds around 200 khz, the tolerance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed is 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801b 300 0x8024 200 0x8035 100 0x00a0 50 0x0140 20 0x0320 ]??? ^ d z d ^ z ^ z w / ? ? z w z ^ s z /? s z /? ^ d d?? >?? ^ ^ > ? (~ ^ ? ?~ ^ ^ > ? z~ ^ d ? ~ ^ < , ? ~ ^ < > ? ?~ ^ ? ?~ ^ < ? (~ ^ < ? z~ ^ ^ d z d z w d ^ d z d ? ?~ ^ d ? ?~ ^ d k ^ d k w ? ?~ ^ d w ^ d k electrical characteristics stm32l100rc 80/105 docid024995 rev 3 spi characteristics unless otherwise specified, the parameters given in the following table are derived from tests performed under the conditions summarized in table 12 . refer to section 6.3.12: i/o current injection characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 48. spi characteristics (1) symbol parameter conditions min max (2) unit f sck 1/t c(sck) spi clock frequency master mode - 16 mhz slave mode - 16 slave transmitter - 12 (3) t r(sck) (2) t f(sck) (2) spi clock rise and fall time capacitive load: c = 30 pf - 6 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) nss setup time slave mode 4t hclk - ns t h(nss) nss hold time slave mode 2t hclk - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode t sck /2 ? 5t sck /2+3 t su(mi) (2) data input setup time master mode 5 - t su(si) (2) slave mode 6 - t h(mi) (2) data input hold time master mode 5 - t h(si) (2) slave mode 5 - t a(so) (4) data output access time slave mode 0 3t hclk t v(so) (2) data output valid time slave mode - 33 t v(mo) (2) data output valid time master mode - 6.5 t h(so) (2) data output hold time slave mode 17 - t h(mo) (2) master mode 0.5 - 1. the characteristics above are given for voltage range 1. 2. guaranteed by characterization results, not tested in production. 3. the maximum spi clock frequency in slave transmitter mode is given for an spi slave input clock duty cycle (ducy(sck)) ranging between 40 to 60%. 4. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. docid024995 rev 3 81/105 stm32l100rc 96 figure 17. spi timing diagram - slave mode and cpha = 0 figure 18. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. d l f ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e e ^ ^ ]v?? ? ^ h~ e ^ ^ ?~ ^ < ?z~ e ^ ^ ?~ ^ k ?~ ^ < ,?~ ^ < > ?~ ^ k ?z~ ^ k ??~ ^ <?(~ ^ < ?]?~ ^ k ??~ ^ / ?z~ ^ / d l ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e ? ^ h~ e ^ ^ ? ~ ^ < ? z~ e ^ ^ ? ~ ^ k ? ~ ^ > , ? ~ ^ > > ? ~ ^ k ? z~ ^ k ? ?~ ^ > ? (~ ^ > ? ]?~ ^ k ? ?~ ^ / ? z~ ^ / e ^ ^ ]v?? electrical characteristics stm32l100rc 82/105 docid024995 rev 3 figure 19. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. d l 6 & . , q s x w & 3 + $ 0 2 6 , 2 8 7 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ 0 6 % , 1 0 6 % 2 8 7 % , 7 , 1 / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & / + w z 6 & / / w u 6 & / w i 6 & / w k 0 , + l j k 6 & . , q s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 docid024995 rev 3 83/105 stm32l100rc 96 usb characteristics the usb interface is usb-if certified (full speed). figure 20. usb timings: definition of data signal rise and fall time table 49. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s table 50. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage - 3.0 3.6 v v di (2) 2. guaranteed by characterization results, not tested in production. differential input sensitivity i(usb_dp, usb_dm) 0.2 - v v cm (2) differential common mode range includes v di range 0.8 2.5 v se (2) single ended receiver threshold - 1.3 2.0 output levels v ol (3) 3. guaranteed by test in production. static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb drivers. - 0.3 v v oh (3) static output level high r l of 15 k to v ss (4) 2.8 3.6 table 51. usb: full speed electrical characteristics driver characteristics (1) symbol parameter conditions min max unit t r rise time (2) c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns d l w i 6 6 w u 9 & 5 6 9 ' l i i h u h q w l d o g d w d o l q h v & u r v v r y h u s r l q w v electrical characteristics stm32l100rc 84/105 docid024995 rev 3 i2s characteristics note: refer to the i2s section of the product reference manual for more details about the sampling frequency (fs), f mck , f ck and d ck values. these values reflect only the digital peripheral behavior, source clock precision might slightly change them. dck depends mainly on the t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v 1. guaranteed by design, not tested in production. 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). table 52. i2s characteristics symbol parameter conditions min max unit f mck i2s main clock output 256 x 8k 256xfs (1) 1. the maximum for 256xfs is 8 mhz mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver, 48khz 30 70 % t r(ck) i2s clock rise time capacitive load cl=30pf - 8 ns t f(ck) i2s clock fall time 8 t v(ws) ws valid time master mode 4 24 t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 15 - t h(ws) ws hold time slave mode 0 - t su(sd_mr) data input setup time master receiver 8 - t su(sd_sr) data input setup time slave receiver 9 - t h(sd_mr) data input hold time master receiver 5 - t h(sd_sr) slave receiver 4 - t v(sd_st) data output valid time slave transmitter (after enable edge) -64 t h(sd_st) data output hold time slave transmitter (after enable edge) 22 - t v(sd_mt) data output valid time master transmitter (after enable edge) -12 t h(sd_mt) data output hold time master transmitter (after enable edge) 8- table 51. usb: full speed electrical characteristics (continued) driver characteristics (1) symbol parameter conditions min max unit docid024995 rev 3 85/105 stm32l100rc 96 odd bit value, digital contribution leads to a min of (i2sdiv/(2*i2sdiv+odd) and a max of (i2sdiv+odd)/(2*i2sdiv+odd). fs max is supported for each mode/condition. figure 21. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. figure 22. i 2 s master timing diagram (philips protocol) (1) 1. guaranteed by characterization results, not tested in production. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t electrical characteristics stm32l100rc 86/105 docid024995 rev 3 6.3.17 12-bit adc characteristics unless otherwise specified, the parameters given in table 54 are guaranteed by design. table 53. adc clock frequency symbol parameter conditions min max unit f adc adc clock frequency voltage range 1 & 2 2.4 v v dda 3.6 v v ref+ = v dda 0.480 16 mhz v ref+ < v dda v ref+ > 2.4 v 8 v ref+ < v dda v ref+ 2.4 v 4 1.8 v v dda 2.4 v v ref+ = v dda 8 v ref+ < v dda 4 voltage range 3 4 table 54. adc characteristics symbol parameter conditions min typ max unit v dda power supply - 1.8 - 3.6 v v ref+ positive reference voltage - 1.8 (1) -v dda v ref- negative reference voltage - - v ssa - i vdda current on the v dda input pin - - 1000 1450 a i vref (2) current on the v ref input pin peak - 400 700 average 450 v ain conversion voltage range (3) -0 (4) -v ref+ v f s 12-bit sampling rate direct channels - - 1 msps multiplexed channels - - 0.76 10-bit sampling rate direct channels - - 1.07 msps multiplexed channels - - 0.8 8-bit sampling rate direct channels - - 1.23 msps multiplexed channels - - 0.89 6-bit sampling rate direct channels - - 1.45 msps multiplexed channels - - 1 docid024995 rev 3 87/105 stm32l100rc 96 t s (5) sampling time direct channels 2.4 v v dda 3.6 v 0.25 - - s multiplexed channels 2.4 v v dda 3.6 v 0.56 - - direct channels 1.8 v v dda 2.4 v 0.56 - - multiplexed channels 1.8 v v dda 2.4 v 1-- - 4 - 384 1/f adc t conv total conversion time (including sampling time) f adc = 16 mhz 1 - 24.75 s - 4 to 384 (sampling phase) +12 (successive approximation) 1/f adc c adc internal sample and hold capacitor direct channels - 16 - pf multiplexed channels - - f trig external trigger frequency regular sequencer 12-bit conversions - - tconv+1 1/f adc 6/8/10-bit conversions - - tconv 1/f adc f trig external trigger frequency injected sequencer 12-bit conversions - - tconv+2 1/f adc 6/8/10-bit conversions - - tconv+1 1/f adc r ain (6) signal source impedance - - 50 k t lat injection trigger conversion latency f adc = 16 mhz 219 - 281 ns - 3.5 - 4.5 1/f adc t latr regular trigger conversion latency f adc = 16 mhz 156 - 219 ns - 2.5 - 3.5 1/f adc t stab power-up time - - - 3.5 s 1. the vref+ input can be grounded if neither the adc nor the dac are used (this allows to shut down an external voltage reference). 2. the current consumption through vref is composed of two parameters: - one constant (max 300 a) - one variable (max 400 a), only during sampling time + 2 first conversion pulses so, peak consumption is 300+400 = 700 a and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 a at 1msps 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pin descriptions for further details. 4. v ssa or v ref- must be tied to ground. 5. minimum sampling time is reached for an external input impedance limited to a value as defined in table 56: maximum source impedance rain max 6. external impedance has another high value limitation when using short sampling time as defined in table 56: maximum source impedance rain max table 54. adc characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l100rc 88/105 docid024995 rev 3 table 55. adc accuracy (1)(2) symbol parameter test conditions min (3) typ max (3) unit et total unadjusted error 2.4 v v dda 3.6 v 2.4 v v ref+ 3.6 v f adc = 8 mhz, r ain = 50 t a = -40 to 105 c -4 lsb eo offset error - 1 2 eg gain error - 1.5 3.5 ed differential linearity error - 1 2 el integral linearity error - 3 enob effective number of bits 2.4 v v dda 3.6 v v dda = v ref+ f adc = 16 mhz, r ain = 50 t a = -40 to 105 c f input =10khz 9.2 10 - bits sinad signal-to-noise and distortion ratio 57.5 62 - db snr signal-to-noise ratio 57.5 62 - thd total harmonic distortion - -70 -65 enob effective number of bits 1.8 v v dda 2.4 v v dda = v ref+ f adc = 8 mhz or 4 mhz, r ain = 50 t a = -40 to 105 c f input =10khz 9.2 10 - bits sinad signal-to-noise and distortion ratio 57.5 62 - db snr signal-to-noise ratio 57.5 62 - thd total harmonic distortion - -70 -65 et total unadjusted error 2.4 v v dda 3.6 v 1.8 v v ref+ 2.4 v f adc = 4 mhz, r ain = 50 t a = -40 to 105 c - 4 6.5 lsb eo offset error - 2 4 eg gain error - 4 6 ed differential linearity error - 1 2 el integral linearity error - 1.5 3 et total unadjusted error 1.8 v v dda 2.4 v 1.8 v v ref+ 2.4 v f adc = 4 mhz, r ain = 50 t a = -40 to 105 c -23 lsb eo offset error - 1 1.5 eg gain error - 1.5 2 ed differential linearity error - 1 2 el integral linearity error - 1 1.5 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.12 does not affect the adc accuracy. 3. guaranteed by characterization results, not tested in production. docid024995 rev 3 89/105 stm32l100rc 96 figure 23. adc accuracy characteristics figure 24. typical connection diagram using the adc 1. refer to table 56: maximum source impedance rain max for the value of r ain and table 54: adc characteristics for the value of c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o x q d m x v w h g h u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q i h u f x u y h v ( 2 2 i i v h w h u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l v l w r q d q g w k h i l u v w l g h d o r q h ( * * d l q h u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o o l q h d u l w \ h u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g l g h d o r q h ( / , q w h j u d o o l q h d u l w \ h u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q r q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ d l e 9 5 ( ) r u g h s h q g l q j r q s d f n d j h @ 9 ' ' $ > / 6 % , ' ( $ / d l h 6 7 0 / [ [ 9 ' ' $ $ , 1 [ , / ? q $ 5 $ , 1 & s d u d v l w l f 9 $ , 1 e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u electrical characteristics stm32l100rc 90/105 docid024995 rev 3 figure 25. maximum dynamic current consumption on v ref+ supply pin during adc conversion general pcb design guidelines power supply decoupling should be performed as shown in figure 7 . the applicable procedure depends on whether v ref+ is connected to v dda or not. the 100 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. adc clock sampling (n cycles) conversion (12 cycles) i ref+ 300a 700a table 56. maximum source impedance r ain max (1) ts ( s) r ain max (k ) ts (cycles) f adc = 16 mhz (2) multiplexed channels direct channels 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 0.25 not allowed not allowed 0.7 not allowed 4 0.5625 0.8 not allowed 2.0 1.0 9 1 2.0 0.8 4.0 3.0 16 1.5 3.0 1.8 6.0 4.5 24 3 6.8 4.0 15.0 10.0 48 6 15.0 10.0 30.0 20.0 96 12 32.0 25.0 50.0 40.0 192 24 50.0 50.0 50.0 50.0 384 1. guaranteed by design, not tested in production. 2. number of samples calculated for f adc = 16 mhz. for f adc = 8 and 4 mhz the number of sampling cycles can be reduced with respect to the minimum sampling time ts ( s), docid024995 rev 3 91/105 stm32l100rc 96 6.3.18 dac electrical specifications data guaranteed by design, not tested in production, unless otherwise specified. table 57. dac characteristics symbol parameter conditions min typ max unit v dda analog supply voltage 1.8 - 3.6 v v ref+ reference supply voltage v ref+ must always be below v dda 1.8 - 3.6 v ref- lower reference voltage v ssa i ddvref+ (1) current consumption on v ref+ supply v ref+ = 3.3 v no load, middle code (0x800) - 130 220 a no load, worst code (0x000) - 220 350 i dda (1) current consumption on v dda supply v dda = 3.3 v no load, middle code (0x800) - 210 320 no load, worst code (0xf1c) - 320 520 r l (2) resistive load dac output buffer on 5- - k c l (2) capacitive load - - 50 pf r o output impedance dac output buffer off 12 16 20 k v dac_out voltage on dac_out output dac output buffer on 0.2 - v dda ? 0.2 v dac output buffer off 0.5 - v ref+ ? 1lsb mv dnl (1) differential non linearity (3) c l 50 pf, r l 5 k dac output buffer on - 1.5 3 lsb no r l , c l 50 pf dac output buffer off - 1.5 3 inl (1) integral non linearity (4) c l 50 pf, r l 5 k dac output buffer on -2 4 no r l , c l 50 pf dac output buffer off -2 4 offset (1) offset error at code 0x800 (5) c l 50 pf, r l 5 k dac output buffer on - 10 25 no r l , c l 50 pf dac output buffer off -5 8 offset1 (1) offset error at code 0x001 (6) no r l , c l 50 pf dac output buffer off - 1.5 5 electrical characteristics stm32l100rc 92/105 docid024995 rev 3 doffset/dt (1) offset error temperature coefficient (code 0x800) v dda = 3.3v v ref+ = 3.0v t a = 0 to 50 c dac output buffer off -20 -10 0 v/c v dda = 3.3v v ref+ = 3.0v t a = 0 to 50 c dac output buffer on 020 50 gain (1) gain error (7) c l 50 pf, r l 5 k dac output buffer on - +0.1 / -0.2% +0.2 / -0.5% % no r l , c l 50 pf dac output buffer off - +0 / -0.2% +0 / -0.4% dgain/dt (1) gain error temperature coefficient v dda = 3.3v v ref+ = 3.0v t a = 0 to 50 c dac output buffer off -10 -2 0 v/c v dda = 3.3v v ref+ = 3.0v t a = 0 to 50 c dac output buffer on -40 -8 0 tue (1) total unadjusted error c l 50 pf, r l 5 k dac output buffer on -12 30 lsb no r l , c l 50 pf dac output buffer off -8 12 t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till dac_out reaches final value 1lsb c l 50 pf, r l 5 k -7 12 s update rate max frequency for a correct dac_out change (95% of final value) with 1 lsb variation in the input code c l 50 pf, r l 5 k - - 1 msps t wakeup wakeup time from off state (setting the enx bit in the dac control register) (8) c l 50 pf, r l 5 k -9 15 s psrr+ v dda supply rejection ratio (static dc measurement) c l 50 pf, r l 5 k - -60 -35 db 1. data based on characterization results. 2. connected between dac_out and v ssa . 3. difference between two consecutive codes - 1 lsb. table 57. dac characteristics (continued) symbol parameter conditions min typ max unit docid024995 rev 3 93/105 stm32l100rc 96 figure 26. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.19 operational amplifier characteristics 4. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. 5. difference between the value measured at code (0x800) and the ideal value = v ref+ /2. 6. difference between the value measured at code (0x001) and the ideal value. 7. difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xfff when buffer is off, and from code giving 0.2 v and (v dda ? 0.2) v when buffer is on. 8. in buffered mode, the output can overshoot above the final value for low input code (starting from min value). 5 / & / % x i i h u h g 1 r q e x i i h u h g ' $ & ' $ & b 2 8 7 [ % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u a i 6 table 58. operational amplifier characteristics symbol parameter condition (1) min (2) typ max (2) unit cmir common mode input range - 0 - v dd vi offset input offset voltage maximum calibration range --- 15 mv after offset calibration --- 1.5 vi offset input offset voltage drift normal mode - - - 40 v/c low-power mode - - - 80 i ib input current bias dedicated input 75 c --1 na general purpose input --10 i load drive current normal mode - - - 500 a low-power mode - - - 100 i dd consumption normal mode no load, quiescent mode - 100 220 a low-power mode - 30 60 cmrr common mode rejection ration normal mode - - -85 - db low-power mode - - -90 - electrical characteristics stm32l100rc 94/105 docid024995 rev 3 psrr power supply rejection ratio normal mode dc - -85 - db low-power mode - -90 - gbw bandwidth normal mode v dd >2.4 v 400 1000 3000 khz low-power mode 150 300 800 normal mode v dd <2.4 v 200 500 2200 low-power mode 70 150 800 sr slew rate normal mode v dd >2.4 v (between 0.1 v and v dd -0.1 v) - 700 - v/ms low-power mode v dd >2.4 v - 100 - normal mode v dd <2.4 v - 300 - low-power mode - 50 - ao open loop gain normal mode 55 100 - db low-power mode 65 110 - r l resistive load normal mode v dd <2.4 v 4- - k low-power mode 20 - - c l capacitive load - - - 50 pf voh sat high saturation voltage normal mode i load = max or r l = min v dd - 100 -- mv low-power mode v dd -50 - - vol sat low saturation voltage normal mode - - 100 low-power mode - - 50 ? m phase margin - - 60 - gm gain margin - - -12 - db t offtrim offset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy --1-ms t wakeup wakeup time normal mode c l 50 pf, r l 4 k -10- s low-power mode c l 50 pf, r l 20 k -30- 1. operating conditions are limited to junction temperature (0 c to 105 c) when v dd is below 2 v. otherwise to the full ambient temperature range (-40 c to 85 c, -40 c to 105 c). 2. guaranteed by characterization results, not tested in production. table 58. operational amplifier characteristics (continued) symbol parameter condition (1) min (2) typ max (2) unit docid024995 rev 3 95/105 stm32l100rc 96 6.3.20 comparator table 59. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization results, not tested in production. unit v dda analog supply voltage - 1.65 3.6 v r 400k r 400k value - - 400 - k r 10k r 10k value - - 10 - v in comparator 1 input voltage range - 0.6 - v dda v t start comparator startup time - - 7 10 s td propagation delay (2) 2. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. --310 voffset comparator offset - - 3 10 mv d voffset /dt comparator offset variation in worst voltage stress conditions v dda = 3.6 v v in+ = 0 v v in- = v refint t a = 25 c 0 1.5 10 mv/1000 h i comp1 current consumption (3) 3. comparator consumption only. internal reference voltage not included. - - 160 260 na table 60. comparator 2 characteristics symbol parameter conditions min typ max (1) 1. guaranteed by characterization results, not tested in production. unit v dda analog supply voltage - 1.65 - 3.6 v v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay (2) in slow mode 1.65 v v dda 2.7 v - 1.8 3.5 2.7 v v dda 3.6 v - 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v v dda 2.7 v - 0.8 2 2.7 v v dda 3.6 v - 1.2 4 v offset comparator offset error - 4 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda = 3.3v t a = 0 to 50 c v- =v refint , 3/4 v refint , 1/2 v refint , 1/4 v refint . -15 30 ppm /c i comp2 current consumption (3) fast mode - 3.5 5 a slow mode - 0.5 2 electrical characteristics stm32l100rc 96/105 docid024995 rev 3 6.3.21 lcd controller the device embeds a built-in step-up converter to provide a constant lcd reference voltage independently from the v dd voltage. an external capacitor c ext must be connected to the v lcd pin to decouple this converter. 2. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3. comparator consumption only. internal reference voltage (necessary for comparator operation) is not included. table 61. lcd controller characteristics symbol parameter min typ max unit v lcd lcd external voltage - - 3.6 v v lcd0 lcd internal reference voltage 0 - 2.6 - v lcd1 lcd internal reference voltage 1 - 2.73 - v lcd2 lcd internal reference voltage 2 - 2.86 - v lcd3 lcd internal reference voltage 3 - 2.98 - v lcd4 lcd internal reference voltage 4 - 3.12 - v lcd5 lcd internal reference voltage 5 - 3.26 - v lcd6 lcd internal reference voltage 6 - 3.4 - v lcd7 lcd internal reference voltage 7 - 3.55 - c ext v lcd external capacitance 0.1 - 2 f i lcd (1) 1. lcd enabled with 3 v internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no lcd connected. supply current at v dd = 2.2 v - 3.3 - a supply current at v dd = 3.0 v - 3.1 - r htot (2) 2. guaranteed by design, not tested in production. low drive resistive network overall value 5.28 6.6 7.92 m r l (2) high drive resistive network total value 192 240 288 k v 44 segment/common highest level voltage - - v lcd v v 34 segment/common 3/4 level voltage - 3/4 v lcd - v v 23 segment/common 2/3 level voltage - 2/3 v lcd - v 12 segment/common 1/2 level voltage - 1/2 v lcd - v 13 segment/common 1/3 level voltage - 1/3 v lcd - v 14 segment/common 1/4 level voltage - 1/4 v lcd - v 0 segment/common lowest level voltage 0 - - vxx (3) 3. guaranteed by characterization results, not tested in production. segment/common level voltage error t a = -40 to 105 c -- 50 mv docid024995 rev 3 97/105 stm32l100rc 104 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers this device in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. package characteristics stm32l100rc 98/105 docid024995 rev 3 figure 27. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline 1. drawing is not to scale. : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p docid024995 rev 3 99/105 stm32l100rc 104 table 62. lqfp64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 7.500 0.2953 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 7.500 0.2953 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 k 0.0 3.5 7.0 0.0 3.5 7.0 package characteristics stm32l100rc 100/105 docid024995 rev 3 figure 28. recommended footprint 1. dimensions are in millimeters. a i c docid024995 rev 3 101/105 stm32l100rc 104 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. figure 29. thermal resistance suffix 6 table 63. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 46 c/w 0 6 9 7 h p s h u d w x u h ? & 3 ' p : ) r u e l g g h q d u h d 7 - ! 7 - p d [ / 4 ) 3 [ p p package characteristics stm32l100rc 102/105 docid024995 rev 3 figure 30. thermal resistance suffix 7 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 0 6 y 9 7 h p s h u d w x u h ? & 3 ' p : ) r u e l g g h q d u h d 7 - ! 7 - p d [ / 4 ) 3 [ p p docid024995 rev 3 103/105 stm32l100rc 104 8 ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 64. stm32l100rc ordering information scheme example: stm32 l 100 r c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 100: device with lcd pin count r = 64 pins flash memory size c = 256 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105c packing tr = tape and reel no character = tray or tube revision history stm32l100rc 104/105 docid024995 rev 3 9 revision history table 65. document revision history date revision changes 25-jul-2013 1 initial release. 25-june-2014 2 updated electrical characteristics updated the conditions in table 24: low-power mode wakeup timings . removed ambiguity of ?ambient temperature? in the electrical characteristics description. 12-sept-2014 3 updated communication interfaces section including i2s characteristics. updated dmips features in cover page and description section. updated table 7: stm32l100rc pin definitions with additional functions column. updated table 18: current consumption in sleep mode flash on, off mode. updated table: adc maximum source impedance, rain max. docid024995 rev 3 105/105 stm32l100rc 105 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved |
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